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AuthorTopic: Individual Computers Announces Clone-A Project  (Read 8371 times)

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Offline Marco

Re: Individual Computers Announces Clone-A Project
« Reply #75 on: October 14, 2006, 03:51:29 PM »
Holy reimplementation Batman!

Though I would have no interest in one of those joystick things, I do see the possibilities in doing such a thing. Look at how many of those C64-sticks they sold, the revenue from that sort of thing with an Amiga-stick could be used to develop Clone-A further, incorporating ECS, AGA and perhaps further enhancements.

I doubt anything like AAA-compatibility would be doable, mainly since no programs exist for it and the (unfinished) designs are probably in Dave Haynies basement or something but maybe something along the lines of AAA in terms of technical specs.
[color=6666FF]Iu he nesciti, u dia cun l\\\'urbu azurru, di parinti barbari, \\\'ntre u bunu i virtuusu Cimmiriu[/color][/b]
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Offline Egg-Chen

Re: Individual Computers Announces Clone-A Project
« Reply #76 on: October 14, 2006, 03:57:07 PM »
It's a very good news !
I'm waiting for the AGA version. It's OK for me as far as it can run Brilliance 2.0, I will surely buy one !

@Jens
Would it be possible to add one (or two) SID socket like in the C-One to expend the Clone-A audio possibilities ?
Would it be possible to design a Clone-A mother board that fit in a A1200 or better a A600 case ?

Anyway good work and good luck !
 

Offline N7VQM

Re: Individual Computers Announces Clone-A Project
« Reply #77 on: October 14, 2006, 06:38:04 PM »
More dreaming:

*ECS miniITX motherboad with an A3K/4K-style CPU slot complete with INT13
*On-board USB

Yep, I know.  May be too much dreaming there.

Dreaming aside, such a product that included 2 or 3 PCI slots (a Zorro slot is probably asking too much) and a couple nice on-board features like ethernet and maybe USB would be very interesting to me.

If the memory subsystem were fast enough, PC2100 for example, would there even been a need for the Chip/Fast RAM distinction?
\\"...an error of 1 is much less significant in counting the population of the Earth than in counting the occupants of a phone booth.\\" - Michael T. Heath, Scientific Computing...
 

Offline jen-ss

Re: Individual Computers Announces Clone-A Project
« Reply #78 on: October 14, 2006, 09:09:53 PM »
@redrumloa:

Quote

No need to validate your registration to me, I'm not the webmaster. I'm simply questioning because of your constant play on his name. Which if I'm not mistaken, you've possibly even done in your nick. Though I hope I am wrong in my assumption.


Well, I guess somehow jen-ss has a similarity to Jens... till I tell you that it's my gaming nick.  The 'jen' part is (was) the clan (Joint Executive Ninjas; feel free to laugh about it all you want) I was in and the 'ss' part are my initials and not to be mistaken the Nazi elite, please. When the a.org registration asked me to fill in a 'nickname', this is the first thing that came to my mind, probably because of the fact that I used to use it a lot. It's actually supposed to be [J.E.N]-SS, but for some reason I couldn't sign up using that nickname (something to do with forbidden characters?).


Quote

Anyhow I think you are off base by believing many people are losing interest in the MiniMig. There is room for a commercial and a free project. I think more people will appreciate both. I certainly do. This community needs something ,ANYTHING new to use that isn't some non-working overpriced reference with a boing sticker slapped on it.


I never mentioned that people are loosing interest. From my point of view there are two things going on here; people are generally misinformed about the REAL facts of A500 clone development AND anything that Jens Schoenfeldt says quite frankly goes. I feel that I have been observant enough to pick that up, but please do correct me if you think I am wrong. I have nothing at all against Herr Schoenfeldt, but I would like to see people maintain a more of an objective point of view on the Clone-A vs MiniMig matter. You could call it skepticism. People just hear things and seem not to even want to look at or even think twice about the real facts before talking these days.




@ Schoenfeldt:

When will you be releasing more specs and/or facts on the possible Mini-ITX board that you plan to fabricate? I am interested to see what you are making of it! Is it going to be a circuit exact copy of an A500, or are you opting for an single-chip solution similar to that of MiniMig? Am I correct to assume that you are attempting to implementing the core processor (68k) in to the FPGA in the sense of building one out of FPGA logic-gates, or are you opting for an FPGA with ready embedded PPC processor (eg Xilinx Virtex-II/Virtex-4 with integrated IBM PowerPC 405 core)? I am interested to know this because the general assumption in the FPGA world is that it is not worth 'cloning' a 68k processor in terms of the shear number of logic gates needed to successfully do so. It turns out that the 68k is quite a complex piece of work.

Can I also ask you to explain to me why exactly your implementation of an A500 clone can be any smaller than MiniMig aside from integrating the 68k and a MMC controller in to the FPGA? I have given it some thought, but just don't seem to grasp the physics involved.




@N7VQM

Quote

Dreaming aside, such a product that included 2 or 3 PCI slots (a Zorro slot is probably asking too much) and a couple nice on-board features like ethernet and maybe USB would be very interesting to me.


To me it would seem like an obvious step to outfit Clone-A with onboard Ethernet from factory, and I think that the Clone-A development team probably has that covered. Remember that Herr Schoenfeldt did mention that he has a lot of idea's that he is looking to incorporate into Clone-A during his interview with Total Amiga. With regards to the PCI/Zorro slots; Because just about everything is possible with FPGA, it shouldn't be too much trouble to add any of the two later on as long as such expansion possibilities have been taken into consideration during the PCB design phase.


Quote

If the memory subsystem were fast enough, PC2100 for example, would there even been a need for the Chip/Fast RAM distinction?


No. Dennis has already gone as far as utilizing a single synchronous bus running at approx. 7.09 Mhz to replace the two distinct chip-ram and fast-ram busses in MiniMig; no problem.



Thanks all!

jen-ss (Sander)
 

Offline Hans_

Re: Individual Computers Announces Clone-A Project
« Reply #79 on: October 15, 2006, 05:45:49 PM »
Quote

It doesn't matter to me how certain you think you are about how Dennis went about cloning the A500 and creating MiniMig. What does actually really matter to me is that you have your facts all mixed up. Dennis has in fact been cloning the A500 chip-by-chip. If you do not believe me, please feel free to read the 850+ posts in the "Amiga in an FPGA: MiniMig" forum topic OR even contact Dennis on the subject.


Funny, I've been following that thread and I don't recall anything saying that he's been cloning it chip by chip. Sure, he started with the copper coprocessor (which is NOT a chip in it's own right  but a sub-component) and then moved to other parts such as the blitter system. That's the only way to do a project like this. I don't have my facts mixed up at all. Dennis van Weeren has taken an overall behavioural approach. Of course he's implemented each sub-component one-by-one. Just not chip-by-chip. Why would he bother to implement the OCS Agnus first, and then Denise, Gary, etc., when he's trying to replicate the overall behaviour, NOT, the behaviour of individual chips on the board. He was not concerned by the timings of the signals between the individual ICs on the A500 motherboard.

Quote

As for the accuracy of the actual signal timings; I agree that MiniMig's synthesized A500 chip set might be a little off compared to the real thing. This is no big deal in the sense that it is something that can be fixed in a real short window of time. Although I my self have not done any in-depth FPGA programming as of yet, I am certain that it is something that even I could FIX in a matter of hours with a timing diagram of the original A500 handy.


I doubt that someone could fix it in just a few hours. Regardless, if Dennis had the timing info, he could adapt his minimig design to separate into the individual chips if he really wanted to.

Quote

Oh, why is it that the signal timing has to be absolutely correct again? Aside from the bugs, MiniMig runs everything A500, doesn't it? It is a true A500 clone after all! Did I actually hear you say "drop-in chip replacements"? Have you any idea what something like that would cost if production is not on an impressive scale? Wouldn't you rather spend your money on a reasonably priced modern implementation of the A500 than on a relatively expensive chip in the hope that none of the other chips need replacing? I know I would.


Jens suggests that by analysing the timings etc at  a chip-level he should ultimately end up with a more compact design. Added to that, it helps with debugging the design too. I could see an advantage to being able to use some of the old chips when testing/debugging the design. That way you can see the whole thing work, including inter-chip interactions, before you've finished designing the whole system.

Personally I don't care about the inter-chip timing; I don't have an A500 motherboard; and, seeing as the entire design could fit in one FPGA, that's definitely the way to go for a new product (it sounds like Jens Schoenfeld will be doing that too).


One final note: you seem to have got the idea that I think Dennis' work isn't as good as Jens'. Not at all. I like both projects. I'm very interested in the different approaches thay've taken to ultimately try to achieve the same goal. I'm an electrical engineer and I plan to get back into working with FPGAs at some point, so, looking at these various projects could give me some ideas that will be of use later.

Hans
http://hdrlab.org.nz/ - Amiga OS 4 projects, programming articles and more. Home of the RadeonHD driver for Amiga OS 4.x project.
 

Offline Hans_

Re: Individual Computers Announces Clone-A Project
« Reply #80 on: October 15, 2006, 05:56:26 PM »
Quote
Can I also ask you to explain to me why exactly your implementation of an A500 clone can be any smaller than MiniMig aside from integrating the 68k and a MMC controller in to the FPGA? I have given it some thought, but just don't seem to grasp the physics involved.


I'm hoping that he'll answer this question too. Possibly some of the signal timings/characteristics are because of things the original Amiga engineers did in order to keep the chip within the transistor-count budgets of the time. For example, making a signal active low instead of active high could remove a few unneeded gates. That's all I can think of personally.

Hans
http://hdrlab.org.nz/ - Amiga OS 4 projects, programming articles and more. Home of the RadeonHD driver for Amiga OS 4.x project.
 

Offline whabang

Re: Individual Computers Announces Clone-A Project
« Reply #81 on: October 15, 2006, 07:07:55 PM »
If you guys pull this one off, then you are truly teh pwn! :-D
Beating the dead horse since 2002.
 

Offline Donar

Re: Individual Computers Announces Clone-A Project
« Reply #82 on: October 15, 2006, 08:58:34 PM »
jen-ss
Quote
What I would like to know is what distinguishes your "Clone-A" from Dennis's MiniMig


I think Dennis stated that he can not provide us with Hardware for MiniMig, it seems Individual computers can provide hardware for people like me, who are to dumb to create their own 6 layer board with an 75W soldering iron on their wooden workbench.  :lol:

Quote
... build a real-working Amiga 500 with 3 full time programmers probably putting some extreme overtime in to copy the Amiga chip set "1 on 1". What does it get me though?


It is said that the plans for AGA chips are lost, i like the idea that Jens and Oliver at one time, first finishing OCS/ECS  will be able to re- implement AGA on real silicon not FPGA. (I think it should be possible if you know all about the inner workings of the chips, right?). I know AGA is old useless technology, bla, bla, nobody need's it in 2006, and real silicon is too expensive either. But i'm a ignorant....so i don't listen.

If you think i'm crazy - here is the rest... They could also extend AGA and implement some/all of the features of AAA. Yes i know, as before, to little, to late in 2006. But i'm a believer...

The Amiga still won the last Demo competition in 2006. Even with old crappy AGA and an 68060. So give the old lady a new make up and she'll be ready to win the Demo Competition in 2025 also.  :-D
<- Amiga 1260 / CD ->
Looking for:
A1200/CF CFV4/@200,256MB,eAGA,SATA,120GB,AROS :D
 

Offline jen-ss

Re: Individual Computers Announces Clone-A Project
« Reply #83 on: October 15, 2006, 11:35:33 PM »
@Hans:

Quote

Funny, I've been following that thread and I don't recall anything saying that he's been cloning it chip by chip. Sure, he started with the copper coprocessor (which is NOT a chip in it's own right but a sub-component) and then moved to other parts such as the blitter system. That's the only way to do a project like this. I don't have my facts mixed up at all.


It's engineering custom to split a large project up in to manageable subsections in order to maintain a manageable whole. This is also the case when reproducing let's say the A500 to create MiniMig; This is something we both agree upon.

I would like to quote a single sentences posted by Dennis in the "Amiga in FPGA: MiniMig" thread;
Posted on: 2005/12/5 13:46 (This is his very first post!)
"I have been working on this for almost a year now and so far I have the OCS Agnus, Paula, OCS Denise and both the CIA's running in the FPGA." - Here he states the individual chips that he has running in the FPGA. Still sure that you have your facts straight?


Quote

Dennis van Weeren has taken an overall behavioural approach. Of course he's implemented each sub-component one-by-one. Just not chip-by-chip. Why would he bother to implement the OCS Agnus first, and then Denise, Gary, etc., when he's trying to replicate the overall behaviour, NOT, the behaviour of individual chips on the board. He was not concerned by the timings of the signals between the individual ICs on the A500 motherboard.


Signal-timings are actually an integral part of the greater whole you call 'overall behaviour' of a microchip. There is no way in hell an FPGA reimplementation of a specific microchip is going to behave anything like the original if the timings are way off. I know for a fact that Dennis has not spent excessive amounts of his development time producing a "cycle exact" copy of the original chip, which is quite frankly the essential difference between MiniMig's synthesized Amiga custom chips and that of Clone-A. Aside from the fact that MiniMig is not a 100% cycle exact reproduction of the A500 (mainly due to the lack of a logic analyzer), there is no way in hell the synthesized chip timings (talking about the inter-chip timings here) are *off* anything more than a slight error percentage as it does actually run Amiga software after all. If I am not mistaken, Dennis has already fixed some bugs that he had due to timing discrepancies.


Quote

I doubt that someone could fix it in just a few hours. Regardless, if Dennis had the timing info, he could adapt his minimig design to separate into the individual chips if he really wanted to.


Each and every chip has already been individually defined in this project. As long as D's notes on the source code are clear, anyone that is knowledgeable in Verilog could straighten any timing discrepancies out. The project is going to be released under an open-source licence soon, remember?


Quote

Jens suggests that by analysing the timings etc at a chip-level he should ultimately end up with a more compact design. Added to that, it helps with debugging the design too. I could see an advantage to being able to use some of the old chips when testing/debugging the design. That way you can see the whole thing work, including inter-chip interactions, before you've finished designing the whole system.


Jens is WRONG. The size of the design (in verilog, as it doesn't get any smaller than the size of an FPGA and some elementary circuitry outside of that FPGA)  is ultimately down to how smart abstract and efficient the programmer can reproduce the functionality of the original hardware. This design-size we speak of is then expressed in number of gates utilized etc. Strictly keeping to an 'exact' cycle accurate design could actually very well involve some overhead concerning the resources utilized within an FPGA AND unnecessarily increase design complexity. What added benefit would more overhead and added complexity have the project may I ask?


Quote

Personally I don't care about the inter-chip timing


Neither do I.


Quote

seeing as the entire design could fit in one FPGA, that's definitely the way to go for a new product (it sounds like Jens Schoenfeld will be doing that too).


The entire design can already be found in a single FPGA (well, the chip set anyway, next step would be to integrate an 68k or preferably a smaller -in terms of FPGA resources required- equivalent processor, and the disk-controller which Dennis seems to have been too lazy to integrate in the first place). It's called MiniMig. Dennis is actually in the process of developing the first real prototype of the final version (12x12 cm PCB < mini ITX!). I am guessing that if it works like he intends it to, he will call it "final" and release everything to the community (or so I hope!). Yes, that 'Amiga on Chip' does seem to be Herr Schoenfeldt's intention.


Quote

One final note: you seem to have got the idea that I think Dennis' work isn't as good as Jens'. Not at all. I like both projects. I'm very interested in the different approaches they've taken to ultimately try to achieve the same goal.


No Hans, I am not under the impression that you think that D's work is any less impressive of that of Schoenfeldt. I am just afraid of the fact that whatever Jens says quite frankly goes, if it's up to some people here... I would like to stimulate people to start their own thought process instead of believing a multitude of what other people say -blindly-.


Quote

I'm hoping that he'll answer this question too. Possibly some of the signal timings/characteristics are because of things the original Amiga engineers did in order to keep the chip within the transistor-count budgets of the time. For example, making a signal active low instead of active high could remove a few unneeded gates. That's all I can think of personally.


That would mean that the Clone-A design would not be exactly cycle-accurate anymore but 'within operation limits' like MiniMig.

It's been a pleasure talking to you Hans! You mentioned that you where thinking of getting back in to FPGA development? Will you be participating in the further development of MiniMig when the time comes? :-)



@Donar:

Quote

I think Dennis stated that he can not provide us with Hardware for MiniMig, it seems Individual computers can provide hardware for people like me, who are to dumb to create their own 6 layer board with an 75W soldering iron on their wooden workbench.


Actually, I think that Dennis just doesn't want to get into all the hassle paired with the whole mass-production aspect of things and he seems to care about the money involved either, so you are probably right about the fact that Clone-A will provide hardware for the non-technical Amiga users amongst us. We shall see what the future has in store for us.


Quote

It is said that the plans for AGA chips are lost, i like the idea that Jens and Oliver at one time, first finishing OCS/ECS will be able to re- implement AGA on real silicon not FPGA. (I think it should be possible if you know all about the inner workings of the chips, right?). I know AGA is old useless technology, bla, bla, nobody needs it in 2006, and real silicon is too expensive either. But I'm a ignorant....so i don't listen.


I happen to know of some hobbyists that are considering to incorporate AGA in to MiniMig as soon as it's source has been released. It aparently isn't too much of a problem. Ah, Shhhssst! Don't ask!

AGA could be re-implemented on real silicon as long as you do have extensive knowledge (could be documented knowledge) on the inner-workings of the chip; no-problem. It can even be done without the extensive knowledge of the inner-workings (reverse engineering), but would just take longer... Still no problem though.

I don't get it. Why would you say that Jens and Oliver would re-implement AGA on silicon instead of FPGA when Jens clearly stated (in the Total Amiga interview) that he'll try to keep his future hardware reconfigurable (FPGA?). What am I overlooking here?


Quote

If you think i'm crazy - here is the rest... They could also extend AGA and implement some/all of the features of AAA. Yes i know, as before, to little, to late in 2006. But i'm a believer...

The Amiga still won the last Demo competition in 2006. Even with old crappy AGA and an 68060. So give the old lady a new make up and she'll be ready to win the Demo Competition in 2025 also.


Start learning Verilog and warming up those precious hands of yours! 'Believers' like you are destined to be at the heart of projects like these as a driving force. When the old lady wins the demo competitions in 2025, we all know who to thank. I guess that I'll be buying the beer! :-)


jen-ss (Sander)
 

Offline Donar

Re: Individual Computers Announces Clone-A Project
« Reply #84 on: October 16, 2006, 08:22:23 AM »
Hello,

Quote
Actually, I think that Dennis just doesn't want to get into all the hassle paired with the whole mass-production aspect of things and he seems to care about the money involved either.


OK, wanted to say the same but probably failed. So still no Hardware.  :-)

Quote
Why would you say that Jens and Oliver would re-implement AGA on silicon instead of FPGA when Jens clearly stated (in the Total Amiga interview) that he'll try to keep his future hardware reconfigurable (FPGA?). What am I overlooking here?


I meant they could, so you could if you/your friends add AGA to MiniMig. See if you would have asked for a new board with AGA a year before most people would have told you that it is impossible. Look at some (first) Responses to Dennis thread- "You don't happen to be Mick Tinker?" and so on.

So, if Dennis or Jens and Oliver are able to implement it on real silicon the first step is done.

Jens stated that he could come up with a small design, for an Amiga in a Joystick if some investor ask's for it. So i think this would be real silicon then, or also an FPGA? The DTV for example uses an ASIC so i think it's no FPGA.

Synthesizing this FPGA into an ASIC is maybe too much for a hobbyist approach i think...maybe i'm wrong.

Bye
<- Amiga 1260 / CD ->
Looking for:
A1200/CF CFV4/@200,256MB,eAGA,SATA,120GB,AROS :D
 

Offline AJCopland

Re: Individual Computers Announces Clone-A Project
« Reply #85 on: October 16, 2006, 11:01:58 AM »
I'd guess that the reason isnt going down the "ASIC+amiga in a joystick" route without proper funding is that the initial setup cost would be quite high. Or at least beyond his current funding.

I'd like to see an AGA version of MiniMig eventually, mostly because i play a lot of AGA games.

I'm also learning VHDL so that when MiniMig is released i can get it and help out with it development. But hardware coding is a little different to software coding that i'm used too  :crazy:

Offline Schoenfeld

Re: Individual Computers Announces Clone-A Project
« Reply #86 on: October 16, 2006, 11:49:22 AM »
Interesting to see how Schoenfeld-bashing goes on here.

Jen-SS: You're ignoring various facts:

- first of all, please consider writing my name correctly. Single d at the end, not dt.

- it's not three full-time programmers, but two hardware developers on the project - both only part-time.

- Dennis pointed out himself that my approach will produce a smaller design.

- Dennis and I are not competitors. I will even provide hardware for his core to run on. Why didn't anybody read that comment?

- I haven't "copied Dennis' effort". Dennis announced his project early december 2005, where Clone-A was already in the making

Some people might care less about inter-chip-communication. I do care a lot, because it tells me so much about the way the chips work. Being able to communicate with the original chips means that I'm on the right path. This approach leaves no room for errors, where the "could care less" approach leaves freedom for interpretation.

It's also funny to see how many people all of a sudden become hardware experts, just because hardware can be "produced" by writing Verilog code. Let me tell you that this is not the case. You're not becoming a C programmer because you can do a "hello world" in C. Therefore, please take the time to *technically* understand the following (and if you continue bashing, I take it that you're not interested in the truth):

If you're doing your own design and afterwards tweak it to be cycle-accurate, you will most probably end up with a bloated design, so in a way, you're right. Take the example of the "miracle two pixel delay" in Denise that the emulator programmers found out about. If you're doing it cycle-accurate, you have to add a 2-bit delay, which will cost you chip space and routing space.
The trick is to find out what Denise is *really* doing during this 2-cycle delay - apart from delaying. The question "why not output the data when it's already known" must be re-phrased to "why is data not yet ready to be sent to the outputs" - that's why Clone-A will not only use less FPGA space, but also be more compatible by design.

Other things are even Verilog-related. If for example a 10-bit counter value must be compared, you compare the 10-bit value and the counter with a simple expression in the code. No matter how good the compiler and optimizer is, it will always produce a 10-bit comparator, which is correct.

However, on a hardware level, you can reduce things to a minimum if you take other knowledge into account. Let's assume the counter is the horizontal line counter (x-coordinate), and want to generate a signal that (dis-)allows sprite DMA at positions 20 and 772. The Verilog code would be absolutely simple about this, as it's two 10-bit comparators. My approach to the thing is to only compare single bits in order to save FPGA space:
I know that the counter is only counting up, so the number 20 is the first where bits 4 and 2 are set at the same time. My first comparator is only 2 bits instead of 10. That same knowledge used on the number 772: It's the first numer (when counting up) where bits 9,8 and 2 are set at the same time. This comparator is 3 bits wide, so I'm using 5 comparator-inputs where a correct Verilog-implementation would use 20. Saved 75% in this example, which is NOT representative.

I am all for your claim to have people make up their own mind about things. In turn, you should feed them with the correct information, and not just with your way to see the world. If you don't have *all* the information, you know nothing. I explained it on a hardware-level above, but you can also hear it on the radio if you take the song by the Scissor sisters:

I don't feel like dancin'

is a totally different line compared to

I don't feel like dancin' without you.


Jens Schönfeld
 

Offline AJCopland

Re: Individual Computers Announces Clone-A Project
« Reply #87 on: October 16, 2006, 02:45:06 PM »
@Jens Schönfeld
Thanks for posting with an exmaple of why you think you'll be able to make your implementation smaller and more accurate.

Why are you planning (indeed are you at all?) on replicating a 68k processor in the fpga? Wouldn't it make more sense to use an existing seperate processor as the MiniMig is and possibly get it shipping faster (hint hint) :-D

@everyone
And that is another reason to wait for these things to become available before ranting and raving about what they are/will/could be.

No wonder everyone gives up and leaves the Amiga if we flame everyone who does anything like this.

I'm looking forward to seeing both Clone-A AND MiniMig.

Andy

Offline Hans_

Re: Individual Computers Announces Clone-A Project
« Reply #88 on: October 16, 2006, 03:46:29 PM »
@jen-ss
Quote
I would like to quote a single sentences posted by Dennis in the "Amiga in FPGA: MiniMig" thread;
Posted on: 2005/12/5 13:46 (This is his very first post!)
"I have been working on this for almost a year now and so far I have the OCS Agnus, Paula, OCS Denise and both the CIA's running in the FPGA." - Here he states the individual chips that he has running in the FPGA. Still sure that you have your facts straight?

You could read that as saying he did each chip one-by-one. Or, that he's implemented all the functionality that each chip contains. Whether he's separated it out into Agnus, Paula etc. in his design files or separated it into functional elements is not specified. Regardless, it works.

Jens has already replied regarding the advantage he has of analysing the interchip signals and timings so there's nothing for me to add there. I agree that Dennis' timings can't be far off as it's actually running OCS software.

Quote
It's been a pleasure talking to you Hans! You mentioned that you where thinking of getting back in to FPGA development? Will you be participating in the further development of MiniMig when the time comes? :-)


Nice talking to you too. I'd certainly like to participate in further development of the MiniMig when the source is released. I'll need to get my hands on a dev-board first and then get up to speed with Verilog. That shouldn't be too hard as I've already worked with VHDL. The languages have some similarities even if Verilog is supposed to be easier to learn.

Now where did I put those AGA specs...

Hans
http://hdrlab.org.nz/ - Amiga OS 4 projects, programming articles and more. Home of the RadeonHD driver for Amiga OS 4.x project.
 

Offline Schoenfeld

Re: Individual Computers Announces Clone-A Project
« Reply #89 on: October 16, 2006, 06:08:15 PM »
The 68K in an FPGA is necessary to have an Amiga-on-a-chip. Buying the processor is not an option if you're making it a toy - that would be too expensive. Having the processor in the same chip will save a ton of money.

If you want somebody to spend a seven-digit amount on this project, you have to have something really convincing. The Amiga chipset itself, including memory, might be about as much as a 68000 CPU that you're buying from Freescale, and still, it would not be cycle-accurate: The 68HC000 has slightly different timings than the original 68000 processor on a few instructions. Some games don't like that, they require the exact amount of cycles.

Having the 68K CPU inside the chip has advantages that are geared towards getting risk capital:

- less hardware cost
- less problems in getting the hardware (only one manufacturer of silicon)
- less money to spend on patching games (that is: no money!)

For all of you who want to hack into the machine: The 68K processor can always be switched off. How many of you have an A2000 with an accelerator? In that case, the 68000 is sitting there, gathering dust. It doesn't hurt, but for an investor, it's a huge plus.

Some people asked if re-implementing the 68K would violate any patents. It would not, because it's running in my own microcode engine. There's a software layer in between that emulates the 68K. The microcode engine is geared towards cycle-exact emulation - most instructions must be slowed down for the processor to be cycle-accurate. I could also do an emulation layer for x86 instructions, although this would not make any sense.

The best comparison would be the early-startup CPU of the C-One: It executes Z80 code, and it can jump into 6502 subroutines. The same idea is in the works for the 68000 CPU, just on a larger scale (32 bits instead of 8 bits).


Jens Schönfeld