Individual Computers Announces Clone-A Project

[jen-ss]

@ Herr Schoenfeldt:

What I would like to know is what distinguishes your "Clone-A" from Dennis's MiniMig.  Don't get me wrong, I think that it is real neat of you to copy D's initiative and build a real-working Amiga 500 with 3 full time programmers probably putting some extreme overtime in to copy the Amiga chip set "1 on 1". What does it get me though? Why would I choose not to go with a better supported (community wide), faster evolving and especially cheaper (it will be FREE after all!) alternative that is highly customizable/expandable?

What made you decide to do an Amiga 500 instead of let's say an Amiga 3000 anyway? You seem to have the resources to have pulled that off and you wouldn't have any headaches because of a certain open source project that definitely does interfere with your interests. Is that an obvious next step?




@ Mister D (Dennis):

I have been following your progress for a while now and this is actually my very first post as I find that everything I wanted to say has been said by others. I would like to thank you for making the project that you have put a whole years worth of effort into open source. I respect that greatly and am awaiting the initial release so I can take a peek in to what makes MiniMig tick and possibly one day even contribute to the project. Thank you!

[jen-ss]

@jen-ss

Dennis has cloned the entire Amiga on an fpga, Individual have cloned the individual (sorry) custom chips separately. The minimig is nice if you want to run A500 software but Clone-A chips could be dropped into an existing Amiga motherboard or even used as the basis for a brand new one.
That`s how it reads to me anyway.

I am not aware if you have actually been keeping close track of the MiniMig project. I would however like to clarify that in both cases (MiniMig as well as Clone-A) the clones are not really 1 on 1 clones. They are realistically the programmers own implementation of the workings of the chip in question. Why you ask? Let me put this to you as simple as I can possibly put it; Both developers have gone about reverse engineering each and every individual chip in the A500 chipset which is necessary if you want to create a real and above all a functioning A500 'clone'. Both developers don't do anything more than take a look at the data that the chips output as a result of a specific input (it's just that Schoenfeldt has a logic analyzer which basically speeds up this reverse-engineering task) and create their own implementation of the chip. That's right you did not read it wrong: it is their own implementation and not a true 1-on-1 chip clone like Herr Jens Schoenfeldt likes to brag about.

Sure, it would be great to have every single chip-implementation built in to it's own FPGA chip however, the general public do tend to forget that FPGA's are not the cheapest of chips. And why waste money on more FPGA's when you can stuff everything on a single FPGA which probably even benefit the inter-chip communication because of the lack of communication busses that span great lengths and is more sensitive to RFI than the same single-chip solution. I am even guessing that Herr Schoenfeldt will initially release a single chip solution (The ITX 15x15 cm board he was reffering to in the interview)  quite like that of MiniMig (which will infact be a 12x12 cm! board). There is quite frankly not much more space on a 15x15 cm PCB unless the developer likes to create a highly complicated design similar to that of a modern (multilayer) motherboard. Aside from the added cost because of it being a multilayer PCB, this adds enough complexity to make the already present EMI problem more complex than it has to be... Ever heard of "Keeping It Simple" ?


@Frags:

As all the A500 chipset's chips have obviously been individually cloned for the MiniMig, I really don't see the fuss about simply sticking each synthesized A500 chip in to it's individual FPGA. Not that I understand why you would want to do something like that in the first place other than possibly designing a drop-in replacement for specific A500 chips. Anyhow, I really don't understand why you think that MiniMig-code could not be used as a base for a new motherboard A500. I obviously am missing your point.

jen-ss (Sander)

[jen-ss]

@ amiga-3k:

If the price is right, a MiniITX sized Amiga would appeal to me, even if it were just and only OCS/ECS Amiga (Minimig). A littlebit more advanced (Jens' Clone-A MiniITX) would appeal more to me. I can surely do with some space-saving on my desk :-)

Why is is that everyone *THINKS* that Herr Schoenfeldt's A500 implementation is more advanced than MiniMig when this is absolutely not true? I have this itching feeling that Herr Schoenfeldt is the type of salesman that would be able to sell you sand in the dessert. He is great at presenting his products, I must admit.




@Hans:

Actually, Dennis' approach has been to replicate the A500 in a behavioural sense based on reference manuals, software emulator code and observing behaviour of the actual hardware. AFAIK he didn't specifically divide it up into the different chips. Hence, it's not guaranteed that you could replace say the A500 Agnus with a Minimig Agnus equivalent. He didn't have to ensure that the timing of all signals connected to/from Agnus matched the timing of the original chip. The Minimig may be cycle-correct in its overall behaviour, but this doesn't mean that the internal signals have the same timing as the original A500. You'd have to reverse-engineer the signal timings for the individual chip and modify the design to take this into account.

Hans,

It doesn't matter to me how certain you think you are about how Dennis went about cloning the A500 and creating MiniMig. What does actually really matter to me is that you have your facts all mixed up. Dennis has in fact been cloning the A500 chip-by-chip. If you do not believe me, please feel free to read the 850+ posts in the "Amiga in an FPGA: MiniMig" forum topic OR  even contact Dennis on the subject.

As for the accuracy of the actual signal timings; I agree that MiniMig's synthesized A500 chip set might be a little off compared to the real thing. This is no big deal in the sense that it is something that can be fixed in a real short window of time. Although I my self have not done any in-depth FPGA programming as of yet, I am certain that it is something that even I could FIX in a matter of hours with a timing diagram of the original A500 handy.

Oh, why is it that the signal timing has to be absolutely correct again? Aside from the bugs, MiniMig runs everything A500, doesn't it? It is a true A500 clone after all! Did I actually hear you say "drop-in chip replacements"? Have you any idea what something like that would cost if production is not on an impressive scale? Wouldn't you rather spend your money on a reasonably priced modern implementation of the A500 than on a relatively expensive chip in the hope that none of the other chips need replacing? I know I would.

Minimig works, although he's not done with bug-fixing yet.

Jens Schoenfeldt isn't even done with his chip set yet and he has three programmers and a logic analyzer. Ha-Ha. Besides, I am sure that once he too has quite some bugfixing to do. What a joy.



jen-ss (Sander)

[jen-ss]

@redlumloa

Excuse me but did you register specifically to bash Jens?

No, not intentionally no. Well, not unless 'salesman' is a dirty word? I am a reasonable judge of character and have had the great pleasure of meeting Herr Schoenfeldt in person in Maarssen not too long ago, although I am sure that he can't place me because of some other vested interests he might of had at the time. I can assure you that I am not telling tales whenever I use the term "salesman" in conjunction with his name.

The reason that I initially signed up was curiosity on what really is supposed to set apart the Clone-A from the MiniMig (my opinion is that they are different implementations of the same thing, one free one and one with a commercial aim) and the fact that I felt dissatisfied because of the lack of recognition the MiniMig project is receiving after Clone-A was announced publicly, which in my opinion is partially due to the fact that Jens Schoenfeldt has an iconic image in the modern amiga community. I do not think that this is something that you could disagree with me on, or am I wrong to say that?

I must admit that my judgement in the Clone-A vs MiniMig matter could very well be biased due to the fact that Dennis is about to make the best gesture possible; donating hundreds of man hours worth of work on something of great value to the community. I do hope that that is not the case though.

I hope to have validated my registration.

regards,

jen-ss (Sander)

[jen-ss]

@redrumloa:

No need to validate your registration to me, I'm not the webmaster. I'm simply questioning because of your constant play on his name. Which if I'm not mistaken, you've possibly even done in your nick. Though I hope I am wrong in my assumption.

Well, I guess somehow jen-ss has a similarity to Jens... till I tell you that it's my gaming nick.  The 'jen' part is (was) the clan (Joint Executive Ninjas; feel free to laugh about it all you want) I was in and the 'ss' part are my initials and not to be mistaken the Nazi elite, please. When the a.org registration asked me to fill in a 'nickname', this is the first thing that came to my mind, probably because of the fact that I used to use it a lot. It's actually supposed to be [J.E.N]-SS, but for some reason I couldn't sign up using that nickname (something to do with forbidden characters?).

Anyhow I think you are off base by believing many people are losing interest in the MiniMig. There is room for a commercial and a free project. I think more people will appreciate both. I certainly do. This community needs something ,ANYTHING new to use that isn't some non-working overpriced reference with a boing sticker slapped on it.

I never mentioned that people are loosing interest. From my point of view there are two things going on here; people are generally misinformed about the REAL facts of A500 clone development AND anything that Jens Schoenfeldt says quite frankly goes. I feel that I have been observant enough to pick that up, but please do correct me if you think I am wrong. I have nothing at all against Herr Schoenfeldt, but I would like to see people maintain a more of an objective point of view on the Clone-A vs MiniMig matter. You could call it skepticism. People just hear things and seem not to even want to look at or even think twice about the real facts before talking these days.




@ Schoenfeldt:

When will you be releasing more specs and/or facts on the possible Mini-ITX board that you plan to fabricate? I am interested to see what you are making of it! Is it going to be a circuit exact copy of an A500, or are you opting for an single-chip solution similar to that of MiniMig? Am I correct to assume that you are attempting to implementing the core processor (68k) in to the FPGA in the sense of building one out of FPGA logic-gates, or are you opting for an FPGA with ready embedded PPC processor (eg Xilinx Virtex-II/Virtex-4 with integrated IBM PowerPC 405 core)? I am interested to know this because the general assumption in the FPGA world is that it is not worth 'cloning' a 68k processor in terms of the shear number of logic gates needed to successfully do so. It turns out that the 68k is quite a complex piece of work.

Can I also ask you to explain to me why exactly your implementation of an A500 clone can be any smaller than MiniMig aside from integrating the 68k and a MMC controller in to the FPGA? I have given it some thought, but just don't seem to grasp the physics involved.




@N7VQM

Dreaming aside, such a product that included 2 or 3 PCI slots (a Zorro slot is probably asking too much) and a couple nice on-board features like ethernet and maybe USB would be very interesting to me.

To me it would seem like an obvious step to outfit Clone-A with onboard Ethernet from factory, and I think that the Clone-A development team probably has that covered. Remember that Herr Schoenfeldt did mention that he has a lot of idea's that he is looking to incorporate into Clone-A during his interview with Total Amiga. With regards to the PCI/Zorro slots; Because just about everything is possible with FPGA, it shouldn't be too much trouble to add any of the two later on as long as such expansion possibilities have been taken into consideration during the PCB design phase.

If the memory subsystem were fast enough, PC2100 for example, would there even been a need for the Chip/Fast RAM distinction?

No. Dennis has already gone as far as utilizing a single synchronous bus running at approx. 7.09 Mhz to replace the two distinct chip-ram and fast-ram busses in MiniMig; no problem.



Thanks all!

jen-ss (Sander)

[jen-ss]

@Hans:

Funny, I've been following that thread and I don't recall anything saying that he's been cloning it chip by chip. Sure, he started with the copper coprocessor (which is NOT a chip in it's own right but a sub-component) and then moved to other parts such as the blitter system. That's the only way to do a project like this. I don't have my facts mixed up at all.

It's engineering custom to split a large project up in to manageable subsections in order to maintain a manageable whole. This is also the case when reproducing let's say the A500 to create MiniMig; This is something we both agree upon.

I would like to quote a single sentences posted by Dennis in the "Amiga in FPGA: MiniMig" thread;
Posted on: 2005/12/5 13:46 (This is his very first post!)
"I have been working on this for almost a year now and so far I have the OCS Agnus, Paula, OCS Denise and both the CIA's running in the FPGA." - Here he states the individual chips that he has running in the FPGA. Still sure that you have your facts straight?

Dennis van Weeren has taken an overall behavioural approach. Of course he's implemented each sub-component one-by-one. Just not chip-by-chip. Why would he bother to implement the OCS Agnus first, and then Denise, Gary, etc., when he's trying to replicate the overall behaviour, NOT, the behaviour of individual chips on the board. He was not concerned by the timings of the signals between the individual ICs on the A500 motherboard.

Signal-timings are actually an integral part of the greater whole you call 'overall behaviour' of a microchip. There is no way in hell an FPGA reimplementation of a specific microchip is going to behave anything like the original if the timings are way off. I know for a fact that Dennis has not spent excessive amounts of his development time producing a "cycle exact" copy of the original chip, which is quite frankly the essential difference between MiniMig's synthesized Amiga custom chips and that of Clone-A. Aside from the fact that MiniMig is not a 100% cycle exact reproduction of the A500 (mainly due to the lack of a logic analyzer), there is no way in hell the synthesized chip timings (talking about the inter-chip timings here) are *off* anything more than a slight error percentage as it does actually run Amiga software after all. If I am not mistaken, Dennis has already fixed some bugs that he had due to timing discrepancies.

I doubt that someone could fix it in just a few hours. Regardless, if Dennis had the timing info, he could adapt his minimig design to separate into the individual chips if he really wanted to.

Each and every chip has already been individually defined in this project. As long as D's notes on the source code are clear, anyone that is knowledgeable in Verilog could straighten any timing discrepancies out. The project is going to be released under an open-source licence soon, remember?

Jens suggests that by analysing the timings etc at a chip-level he should ultimately end up with a more compact design. Added to that, it helps with debugging the design too. I could see an advantage to being able to use some of the old chips when testing/debugging the design. That way you can see the whole thing work, including inter-chip interactions, before you've finished designing the whole system.

Jens is WRONG. The size of the design (in verilog, as it doesn't get any smaller than the size of an FPGA and some elementary circuitry outside of that FPGA)  is ultimately down to how smart abstract and efficient the programmer can reproduce the functionality of the original hardware. This design-size we speak of is then expressed in number of gates utilized etc. Strictly keeping to an 'exact' cycle accurate design could actually very well involve some overhead concerning the resources utilized within an FPGA AND unnecessarily increase design complexity. What added benefit would more overhead and added complexity have the project may I ask?

Personally I don't care about the inter-chip timing

Neither do I.

seeing as the entire design could fit in one FPGA, that's definitely the way to go for a new product (it sounds like Jens Schoenfeld will be doing that too).

The entire design can already be found in a single FPGA (well, the chip set anyway, next step would be to integrate an 68k or preferably a smaller -in terms of FPGA resources required- equivalent processor, and the disk-controller which Dennis seems to have been too lazy to integrate in the first place). It's called MiniMig. Dennis is actually in the process of developing the first real prototype of the final version (12x12 cm PCB < mini ITX!). I am guessing that if it works like he intends it to, he will call it "final" and release everything to the community (or so I hope!). Yes, that 'Amiga on Chip' does seem to be Herr Schoenfeldt's intention.

One final note: you seem to have got the idea that I think Dennis' work isn't as good as Jens'. Not at all. I like both projects. I'm very interested in the different approaches they've taken to ultimately try to achieve the same goal.

No Hans, I am not under the impression that you think that D's work is any less impressive of that of Schoenfeldt. I am just afraid of the fact that whatever Jens says quite frankly goes, if it's up to some people here... I would like to stimulate people to start their own thought process instead of believing a multitude of what other people say -blindly-.

I'm hoping that he'll answer this question too. Possibly some of the signal timings/characteristics are because of things the original Amiga engineers did in order to keep the chip within the transistor-count budgets of the time. For example, making a signal active low instead of active high could remove a few unneeded gates. That's all I can think of personally.

That would mean that the Clone-A design would not be exactly cycle-accurate anymore but 'within operation limits' like MiniMig.

It's been a pleasure talking to you Hans! You mentioned that you where thinking of getting back in to FPGA development? Will you be participating in the further development of MiniMig when the time comes? :-)



@Donar:

I think Dennis stated that he can not provide us with Hardware for MiniMig, it seems Individual computers can provide hardware for people like me, who are to dumb to create their own 6 layer board with an 75W soldering iron on their wooden workbench.

Actually, I think that Dennis just doesn't want to get into all the hassle paired with the whole mass-production aspect of things and he seems to care about the money involved either, so you are probably right about the fact that Clone-A will provide hardware for the non-technical Amiga users amongst us. We shall see what the future has in store for us.

It is said that the plans for AGA chips are lost, i like the idea that Jens and Oliver at one time, first finishing OCS/ECS will be able to re- implement AGA on real silicon not FPGA. (I think it should be possible if you know all about the inner workings of the chips, right?). I know AGA is old useless technology, bla, bla, nobody needs it in 2006, and real silicon is too expensive either. But I'm a ignorant....so i don't listen.

I happen to know of some hobbyists that are considering to incorporate AGA in to MiniMig as soon as it's source has been released. It aparently isn't too much of a problem. Ah, Shhhssst! Don't ask!

AGA could be re-implemented on real silicon as long as you do have extensive knowledge (could be documented knowledge) on the inner-workings of the chip; no-problem. It can even be done without the extensive knowledge of the inner-workings (reverse engineering), but would just take longer... Still no problem though.

I don't get it. Why would you say that Jens and Oliver would re-implement AGA on silicon instead of FPGA when Jens clearly stated (in the Total Amiga interview) that he'll try to keep his future hardware reconfigurable (FPGA?). What am I overlooking here?

If you think i'm crazy - here is the rest... They could also extend AGA and implement some/all of the features of AAA. Yes i know, as before, to little, to late in 2006. But i'm a believer...

The Amiga still won the last Demo competition in 2006. Even with old crappy AGA and an 68060. So give the old lady a new make up and she'll be ready to win the Demo Competition in 2025 also.

Start learning Verilog and warming up those precious hands of yours! 'Believers' like you are destined to be at the heart of projects like these as a driving force. When the old lady wins the demo competitions in 2025, we all know who to thank. I guess that I'll be buying the beer! :-)


jen-ss (Sander)

[jen-ss]

Three...Two...One... Breathe.


@Schoenfeld (no trailing ' t', sorry about that..):

It's also funny to see how many people all of a sudden become hardware experts ... Saved 75% in this example, which is NOT representative.

Even though you seem to understand the physics of an intelligent design (hardware/software), you still argue that a 100% cycle exact re-implementation of the Amiga chip set will in fact aid in creating a smaller design. A smaller design is the direct result of an intelligent design process and NOT that of a 100% cycle exact re-implementation. I am completely flabbergasted about you even proposing such a thing when you your self give a perfect example of intelligent design & programming in action (your approach on the comparator issue). Especially as you are so bold as to utter harsh word about it being funny that people all of a sudden become hardware experts just because "hardware' can be produced by writing Verilog. That was a definite 'under the belt' blow. There is no reason to become all personal now Mr 'hardware expert', is there? ;-) Let's just stick to fact and leave fiction be.

I am all for your claim to have people make up their own mind about things. In turn, you should feed them with the correct information, and not just with your way to see the world.

I am glad that you are supportive of my quest to get people to evaluate the information they receive from others. I can assure you that I am trying my best to feed people with all the 'untainted' information that I can get my hands on. From your perspective it might look like I am enjoying a complete Jens Schoenfeld (look, not trailing 't' again, I am finally starting to get the hang of it!) bashing fest; which is not the case. I am not looking to start any personal vendetta or unnecessary problem with you or anyone for that matter. I am however looking to feed people raw facts to the best of my abilities and try and review every bit of information before I post. I am still only human, but then again; so are you! And if there is one lesson that time has taught us, then it's that ALL humans make mistakes. I find it shameful that people (generally that could be classified as loyal followers of which you have many) believe almost everything you say to be fact -period-, even though this isn't always the case. I wish that they all would carefully scrutinize all information perceived. There's no pain in that, is there?

The 68K in an FPGA is necessary to have an Amiga-on-a-chip. Buying the processor is not an option if you're making it a toy - that would be too expensive. Having the processor in the same chip will save a ton of money.

Yes, definitely. An FPGA implementation of the 68k would save something in the region of three euros per board. It amounts to considerable $avings!

Having the 68K CPU inside the chip has advantages that are geared towards getting risk capital:

- less hardware cost
- less problems in getting the hardware (only one manufacturer of silicon)
- less money to spend on patching games (that is: no money!)

You will find that I agree with you on the first two points. I don't quite understand #3 however. Am I correct in assuming that you mean to say that using an original 68k, be it a physical one or it's FPGA re-implementation, will save you on patching games all together in the sense of the games being 100% compatible, or am I overlooking something here?  

If you want somebody to spend a seven-digit amount on this project, you have to have something really convincing. The Amiga chip set itself, including memory, might be about as much as a 68000 CPU that you're buying from Freescale, and still, it would not be cycle-accurate: The 68HC000 has slightly different timings than the original 68000 processor on a few instructions. Some games don't like that, they require the exact amount of cycles.

I sometimes ask my self if you know what you are talking about, just like I did when I read the piece of text quoted above. As I recalled it, the 68HC000's functioning was identical to that of the 68000. I looked it up, just in case I was wrong, and was shocked, flabbergasted an quite frankly blown away at the same time, to find that you're telling STORIES again! Check it out: http://www.freescale.com/files/shared/doc/selector_guide/SG1001.pdf on page number 7, under MC68HC000. The 'additional information' field states; and I quote: "Complete pin and timing MC68000 compatibility with a tenth of the power dissipation".
Aside from the fact that the MC68HC000 listed in the brochure does not come as a DIP, the timing should still be identical (completely compatible) as the packaging has absolutely nothing to do with timings. How nasty is that? You should really get your facts straight Herr Schoenfeld.

Anyway... a more important matter; I am guessing that even if these timing discrepancy would exist, they wouldn't really matter because, and I quote you yet again:
 

Some people asked if re-implementing the 68K would violate any patents. It would not, because it's running in my own microcode engine. There's a software layer in between that emulates the 68K. The microcode engine is geared towards cycle-exact emulation - most instructions must be slowed down for the processor to be cycle-accurate.

... because of the magical 'microcode engine' and an original 68k emulating software layer. Am I right? Left? Right... patents? I won't even attempt to go there and presume you have all ready done your fair share of homework and lawyer consultations; more than I have done anyway. :-)

May I ask where you are 'sourcing' the 68k FPGA implementation code from? Would it be from opencores.org? I am assuming that you are not going to waste precious development time/money and resources on designing your own 68k implementation from scratch. Oh, and I definitely would like to hear more about your microcode engine if you care to share with me!. I can't quite envision what it is/does and how it works so I would fancy an all-over... I am guessing that more people might just be as interested as I am.


Herr Schoenfeld, I salute you and await you're reply. :-)



@AJCopland:

No wonder everyone gives up and leaves the Amiga if we flame everyone who does anything like this.

If WE flame? So we're flaming now? How sad is that...



@cv643d:

I think it is a bit sad to see so much bashing when a positive new product like this emerges.

I do not really understand what there is to critique, bash or why write technical comments the length of an essay finding faults, discussing technical matters not important to general end users of the product or bashing the developers. Why cant some people just keep a more positive attitude.

I find that it is good to scrutinize everything, and I mean EVERYTHING. Especially when it comes to new products because it generally ensures some form of quality. Even though not all the 'general end users' are interested in- or have the capability to follow up on the 'technical matters', they're still equally important and never cease to exist. And if I didn't have a positive attitude I would probably of never posted anything to begin with. I enjoy the technical tidbits oh so much! :-)



jen-ss (Sander) signing off. Thanks!

[jen-ss]

First of all, let me state that I have absolutely no interest on revealing any personal and/or professional details on my self that could possibly indiscriminate my person (be used against me). I am however professionally involved in the field of engineering (electrical/mechanical) and currently specialize in the development of advanced autonomous control systems. This is as far as I can go because of the serious repercussions I would face if I would reveal any information considered classified. Don't worry, I don't expect you to understand.

No, as a matter of fact. I don't think I would be attending any of your (recent) Clone-A demonstrations. I have no reason to believe that what you want to achieve is impossible and will await the finished product patiently. :-)

The real world is different from what datasheets promise. If a datasheet is talking about "same timing", it probably talks about the same bus timing. I won't question that, but if you're talking about timing in computer terms, it's like you're talking screws in cars. A Mercedes will surely use the same screw as a Volkswagen in some spot, but it still does not make them the same. You have to specify *what* screw, which also applies to "timing" in computer terms: Bus timing? Instruction timing? IRQ timing? I was talking about the number of cycles that an instruction takes, and there's a difference on the HC000 that the datasheet does not cover. Hardly anyone will notice, and if one will and reports the error to Freescale, they will ignore it. I have written extensive eMails to Freescale because I found a bad error in the 68030 manual, but they're all unanswered as of today.

Jens, calm down. Every respectable engineer knows that data sheets should not be taken for granted. Actually the 68000 vs 68HC000 compatibility issue has just as little to do with data sheets as it has to do with screws in cars. Fact is that even if there was an obvious timing discrepancy, Freescale would be compelled to denote it's existence as their processors are used in many application critical applications, both commercially as well as government operated. Fact is that if there really is any actual timing discrepancy (I have reason to doubt the validity of your accusations), they would be well with in normal 68000 operating limits so that the two processors can exist interchangeably. Face it.

Why is is that Dennis is using a  68SEC000, which is an embedded processor that has does actually differ to the original 68k, and doesn't seem to be experiencing any problems running OCS software? This, I am sorry to say, leads me to conclude that your claims are in fact flawed and probably no more than a part of an elaborate marketing technique that you employ to trap investors. I sure hope that the latter is not fact.


Do you know what is starting to annoy me more than having to argue about technical tidbits?

You're saying that everyone should make up their own mind, yet, you're quoting a single source and claim that it's the truth. You're right that it's the vendor (or at least the company that came after), but this also shows that you have never worked with datasheets to an extent where you encounter errors in the documentation. At the risk of repeating myself: If you don't know all the details, you know nothing.
It's fairly common that chips don't exactly behave the way you'd expect them to behave if you read the datasheet. I started learning about that when I made my first commercial design (the Graffiti), and it continues through all my other designs.

Speaking of experience, I have no idea who I am talking to. Let us know what designs you have done so far, or if you're the Wildstar-kind-of-guy that likes to talk BS to keep others talking. So far, we've seen nice rhetoric and only technical half-truths from you.

The rhetorics remind me of a teacher from California who has too much spare time... No insult, I'm just trying to find out who you are because you claim we met in Maarssen.

The fact that you are bestowing extremely blatant remarks upon me is just plain childish. You are very bold indeed when it comes to telling people that you mean no insult after having spoken nothing else but insults and you seem to have an ego problem. I once thought more of you Jens Schoenfeld, but this is just plain outrageous. If this is the level you wish to proceed at, then you are wasting my time and I am done talking with you.


Have a nice evening.