Welcome, Guest. Please login or register.
Amiga Kit Amiga Store Iridium Banner AMIStore App Store A1200/A600 4xIDE Interface

AuthorTopic: IBM Talks Power5 at Hot Chips Conference  (Read 1094 times)

0 Members and 1 Guest are viewing this topic.

Offline Eric_Z

IBM Talks Power5 at Hot Chips Conference
« on: August 20, 2003, 05:04:40 PM »
As a few of you might know IBM has presented it's
POWER5 CPU and some specs of it at the Hot Chips Conference.

Read the article over at CBR online for a good in depth report.

There's allso a nice summary made, from the presentation, over at Macrumors:



--------------------------------------------------------------------------------

Hi guys, Exponent reporting here live from the HotChips
conference, and IBM is coming up right now with their
Power5 presentation....

Talking about the simultaneos multithreading
implementation in Power5

On target to ship in 04, running in labs now,
 started in 2000

What changed since power4 to get SMT in power5

3 fundamental probs: mem latencies (slow RAM),
branch processing, and execution unit utilization (20-25%
util usually seen in commercial code)

MT is designed to address these three issues

Power5:
130nm, Cu, SOI
Dual processor core
8 way superscalar
SMT core:
-up to 2 virtual procs per real proc
-24% area growth per core for SMT
-"natural" extention to power4 design
-going beyond 2 threads per core diminishes returns

Review of different kinds of Multitreading:
-Single thread has low utilization
-coarse grain multitreading gives a second task to run
when utilization is low
-Fine grain threading: problems with long latencies when
resources are constrained
-SMT: no problems with constrained resources

(tech stuff follows, coming too fast to type)
How do they do SMT? Add a second Program counter,
then register renaming had to be extended.

Group Completion Counter had been extended

haches had associativity increased rather than size (more efficient)

Power5 gives dynamic feedback of shared resources,
and the machine takes action if resources are
constrained - net effect is increased parallelism and
increased thruput.

There are situations where inbalanced thread execution
of threads is preferred - power5 gives more execution
slots to threads with higher priority.

(This kind of runs counter to the idea that with SMT you
get a second virtual processor for free due to resource
constraints, but they're IBM, and I'm not....)

SMT is a mode that doesn't have to be entered into
(I think that's what they're saying)

SMT can make chip-bring-up (i.e. intial chip coming back
from the fab debugging) a pain, so Power5 has goodies to help with this)

Dynamic feedback helps things
Chip can dynamically switch between single threading and SMT

40% execution speed improvements for SMT - good return on 24% increase in area.

SMT impacts are pervasive throught the chip.

AIX, Linux and OS/400 have been booted and running
applications

End of presentation, taking questions

4 threads per real processor doesn't make any sense.
3 threads per real processor might make sense, but
making needed resource changes would be difficult

Didn't see benefit of trace cache.

Speaker "not prepared to comment" on how much power
 went up, or what the increase of area due to SMT
affected frequency.

End of questions