What's so bad about Intel 8086 in technical terms?

[biggun]

x86 compilers can now use a lot of the fancy CISC instructions, which internally in the CPU is just a macro for a set of RISC instructions anyway.

This description is not wrong but also not right.
Under this description every CISC CPU ever made on uses RISC instructions.

For example:
The 68000 was a CISC CPU.
The 68000 uses microcode for each instruction.
The "micro-code" pieces can be regarded as RISC.
This means the 68000 did for an ADD (mem),Reg in micocode
* calc EA
* load mem, to temp
* add tmp to reg

So was the 68000 already a RISC chip?

[biggun]

No, microcode isn't like RISC. It's just a table that the cpu uses as part of running the standard opcodes.

I know what Mico-code is.

But where do you know that the microcode lines are not like RISC?
Mircrocode is list of micro-instruction - each one them the CPU can do in a single cycle.
Where is the difference to what the "Pentium Pro" does?

If you call a Pentium-Pro a RISC CPU with CISC decoder -
why don't you call a 68_000 the same?

Modern CISC gives you the best of both worlds, because you can completely redefine your RISC architecture every time but you still have

This has nothing to do with modern CISC.
The instructions the programmer see are always a "compressed" form of the internal signals a CPU needs and uses.

This means the orignal 68_000 might internally use 80bit wide instructions.
But the programmer sees only a 16bit word.

The 68010 might already have changed his internal structure slightly and might have 70bits or 85 bits.

A RISC like POWERPC has internally also totally different signals than the programmer uses as opcodes. And every different PPC chip might have slightly different internal signals.

This means every CPU does a decoding from instruction obcodes to internal signals.
And the internal design is different with every CPU generation.

This concept of translation CISC opcodes to is internal format is not new
Every CISC CPU did this since the ice-age.

[biggun]

Does it really actually write the sequence to an internal writable control store?.

Chip like Pentium Pro / Pentium 2, AMD K6, Pentium 3 etc - Do not do this
They just execute the code - just like the 68_000 did.

What these CPU's like Pentium Pro, do is "marking" Super Scalar possibilities in the ICache.
Btw 68K Apollo / Phoenix do the same.

Newer Cores like P4 Netburst started to write traces caches where they cache micro-ops.
But not all new cores do this. The uops caches are expensive in hardware and this concept was
often not used by later chips.

[biggun]

I didn't, I said the CISC instructions were translated into micro-ops at runtime. Translated means that as each instruction is fetched the frontend and then writes a new program and stores it in fast cache ram which the backend then fetches, decodes and executes.

All CISC chips always translated the instructions that the users see in internal signals.
This has to be like this.
In case of multicycle instructions these were often translated into 1 instruction per cycle.

Today many CISC chips have several execution units.
These units could be EA units or ALU unit.
These units could be organized vertically = like in the 68060 or some VIA x86, or Intel ATOM - or horizontally like in some other x86 chips.

Having more units is always good to increase performance.
As you see in the example of the 68060 which did nearly each EA calcultion for free.
Vertically organisation has the advantage of being able to hide the cache latency easierly.

A horizontal unit layout work only well if the core has strong Out of order possibilities. If you want to go out of order - layouting your units horizontally makes this also a little bit easier.


Someone did say "Today all CISC cores are RISC cores with CISC decoder"
I wanted to clear this up.
Today CISC cores are not RISC - they have an advances design thats all.


The method of translating CISC user instructions (what programmer write) to internal execution codes - is not new - this concept is there since the dawn of computer age. Every CISC chip did this.

Some use microcode for this.
Some even use millicode on top of this.
Some hardwired this.
But the translation was and is always there.



Listen I did not want to attack anyone.
But I work as CPU designer for a living.
I just wanted to explain some of the stuff which seemed to cause some confusion here.

[biggun]

@biggun, "But I work as CPU designer for a living." What kind of CPU do you design? I thought that was something only very few companies did..

I work for a us company with a 3 letter name,
that does produce the biggest and most expensive
CISC chips and which produces big and expensive RISC chips.

I created some mainboard chip,
I did work on accelerator chips for the CISC brand,
and did parts of two of the latest big RISC chips.

But my personal evil world domination plans are this:
http://www.apollo-core.com