I didn't, I said the CISC instructions were translated into micro-ops at runtime. Translated means that as each instruction is fetched the frontend and then writes a new program and stores it in fast cache ram which the backend then fetches, decodes and executes.
All CISC chips always translated the instructions that the users see in internal signals.
This has to be like this.
In case of multicycle instructions these were often translated into 1 instruction per cycle.
Today many CISC chips have several execution units.
These units could be EA units or ALU unit.
These units could be organized vertically = like in the 68060 or some VIA x86, or Intel ATOM - or horizontally like in some other x86 chips.
Having more units is always good to increase performance.
As you see in the example of the 68060 which did nearly each EA calcultion for free.
Vertically organisation has the advantage of being able to hide the cache latency easierly.
A horizontal unit layout work only well if the core has strong Out of order possibilities. If you want to go out of order - layouting your units horizontally makes this also a little bit easier.
Someone did say "Today all CISC cores are RISC cores with CISC decoder"
I wanted to clear this up.
Today CISC cores are not RISC - they have an advances design thats all.
The method of translating CISC user instructions (what programmer write) to internal execution codes - is not new - this concept is there since the dawn of computer age. Every CISC chip did this.
Some use microcode for this.
Some even use millicode on top of this.
Some hardwired this.
But the translation was and is always there.
Listen I did not want to attack anyone.
But I work as CPU designer for a living.
I just wanted to explain some of the stuff which seemed to cause some confusion here.