hppacito wrote:
If the new eproms are fast enough (could also be flash), that can be a 3 cycle access, or a 4 cycle access. A shift register can be used to generate the delayed signal.
Just another brain fart..
If you're gonna use faster eproms/flash, then you need to get the /OVR signal to stop Gayle automatically generating DTACK for the old ROM timing. AFAIK, on an A600 that means the old 'upside down PLCC socket' over Gayle.. which kinda blocks Jens' A600 clockport adapter :-(
Anyway, if you use the socket method it'll be easy to take /SPARE_CS and /INT_6 and add a clockport header on your board. (Or for the grand cost of another 50p, use a 2-4 decoder and have upto 4 clockports)
Also, ethernet should be pretty easy too. Use one of the clockports from above, (maybe replacing /SPARE_CS with /NET_CS for quicker read/writes) and use a CS8900 or RTL8019.
EDTP sell kits/modules for both for around $35 that only need INT inverted and the small matter of writing a SANA2 driver.