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Amiga Hardware Issues and discussion / Re: I made a modified accelerator, it works, but has a problem
« Last post by SpeedGeek on April 24, 2024, 02:38:55 PM »I made progress. I think all this just might work out.
I made screenshots with my scope of what is going on with the E signal.
Initial shows the E from processor (yellow), vs the half divided E output of the modified accelerator. This is the condition at the beginning of this thread.
I was able to hide every other E pulse with an AND gate with inputs from two diver flip flops, the resulting E signal is 25/75 duty cycle. This produced a white screen, by itself this was not enough.
Another attempt was to just use the divider output with 50/50 duty cycle, as in Dennis's design, but likewise by itself it produced a white screen.
Last (working) picture shows E from processor (yellow), 1st divider flip flop (green), and the E output from AND of two divider flip flops (pink). There is about 8ns delay of the pink pulse vs yellow, and a 4ns delay relative to green. I was able to boot to Workbench with a physical floppy (Epson SMD-300), but not the Gotek, although I was able to run ATK from Gotek and do the timer tests, they all passed. No game tests because I don't have any on hand on a physical floppy, need to get the Gotek working. I think it's a timing problem, I think I need to shave at least 4ns with faster flip flops, which I don't have on hand, will need to order some. This is all the progress I can make until then.
So what got it working is feeding this E signal into the NOR gate (U4C on the schematic), as well as using this E to trigger the /VPA and /VMA latching (U5B).
I have an idea for how to generate proper 40/60 duty cycle, by doing an AND of the 1st divider flip flop and the E from processor, then XOR with 2nd divider flip flop. The cycle math works out as follows, at 28MHz the period of E the Amiga chipset expects is 40 cycles (4x10), so the 50/50 pulse generated by the divider is 20 cycles. The E pulse from the processor is 4 cycles. By using the circuit I described I cut off 4 cycles from the pulse of 20. The result is a pulse of 16 cycles, which is 40% of the 40 cycle period. I am not going to try this until I get faster divider flip flops because this isn't the source of my problem at the moment.
I kept thinking about this, and what I read in the 68000 datasheet. The datasheet says the beginning of the E period is not guaranteed, so it wouldn't matter if the generated E pulse is delayed by whole cycles. This is likely why this "just works". I did still have a concern whether it's a problem when externally generated E is somewhere else relative to the processor state machine, but I realize the divided E frequency wouldn't coincide with any processor state machine anyway, so it seems this doesn't matter either since I already know that works.
The only reason this sloppy E clock timing works at all is because the 8520 CIA is not a Motorola 6800 peripheral chip. If it was, this 14 MHz accelerator design would fail. Commodore designed these custom chips for the Amiga and using the E clock to drive them somewhat simplified the Amiga's I/O hardware design.
But just because you can sometimes get away with sloppy timing does not means it's often good idea to do so.
The fundamental timing problem is still not corrected because @ 28 MHz the CPU's E clock cycle will end in one 7 MHz clock. A more reliable way to handle this problem is to disable the 68000 E clock CPU cycle by disconnecting VPA and connecting a pull-up resistor. You then add logic to generate VMA when the E clock is low and keep it latched when the E clock is high. Here is some example boolean logic equations:
/VMA = /E * /VPA # /VMA * E
Next you need to generate EDTACK to terminate the cycle:
/EDTACK.D = /AS * /VMA
/DTACK.D = /AS * /EDTACK
NOTE: Both signals are registered on the rising edge of the 7 MHz clock (but you can experiment with the falling edge) and DTACK is a Tri_State signal.
As far as creating the proper 60/40 duty cycle, that's probably not as important as having the E clock at the proper frequency and having the rising edge synchronized with the 7 MHz clock. The main reason to keep the correct duty cycle is performance concerns.
Then when you get the E clock timing problem solved you can worry about the other timing problems listed in my previous post.
