@minator
Refer to
http://news.com.com/2009-1040-251312.html?legacy=cnethttp://www.national.com/news/item/0,1735,329,00.htmlVIA's early Cyrix III (Joshua, Jedi, Gobi) was based on native x86 Cayenne core. In was later dropped in 2000 in favor of Centaur's WinChip/C5/Samuel. After employing Samuel core, VIA was still using Cyrix III label but this was shorten to just 'C3'. The C3 that I’m referring to is the x86 Cayenne core.
National's Cyrix group(before the buyout by VIA in 1999)has Cyrix MIII (M3, Jalapeno core, Mojave),
It's was an out-of-order, decoupled design (translate x86 to uops) and it has 11 stages.
The usage of "and VIA’s C3(from Cyrix M3 core) is based from Cyrix" statement is for Kenny’s performance/power ratio.
KennyR’s statement about Cyrix PR200’s performance/power ratios can be easly reach by today’s VIA C3 MPU. Using Cyrix PR200 as an example of performance/power ratio reference would be considered to be very poor in the light of AMD's Geode NX/16Watt&35Watt grades K7-AXPs, Intel's Pentium M and VIA's C3(Nehemiah).