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estimated price?
I'm curious as to why this would be the case for the Natami CPU designs. It'd require some quite odd design decisions, IMHO.Every "real" 680x0 design since the 68010 has been able to support a fully external MMU just by supporting full recovery after a bus fault and external bus mastering.With those two features in place, the CPU doesn't need to know whether or not the MMU is there or not. The only way the CPU would "notice" the presence of a MMU would be that it'd occasionally lose bus access or get a bus fault if the MMU had a TLB miss or an access violation respectively - if the MMU isn't present, nothing would interfere with memory accesses.Many early MMU designs did this. Sun and others even managed to do this with plain 68000's, though doing this on a 68000 required some pretty nasty "magic" and/or running two 68000's in parallel on the same instruction stream (yikes, but it worked), offset so that you could halt and restart the second CPU when the first caused an access violation (because the trapped instructions are not fully restartable).A MMU design that slowed down the CPU when it's turned off would a be a major design flaw, IMHO, as there's no good reason for that to be the case at all. Most designs with MMU's only ever "lose" cycles due to the presence of the MMU if there's a TLB miss or access violation even when the MMU is on.
