Thanks very much for the response Hattig. I took a look at your link too, thanks for that.
I'm still not entirely certain that I'm understanding this, though. In fact, I'm pretty certain that I'm not. This is how I've interpreted it:
2 clock cycles pass between initially accessing a location in RAM and the data for that location becoming available.
Then, somehow, only 1 clock cycle passes between the next three accesses.
Why is this? Presumably the following three memory access operations will be for different locations so I would have thought that the same delay between access and available data would apply as in the case of the first access?
Also, what is special about the following three memory accesses? Why should a forth consecutive memory access not benefit from the same thing as the third?
And, finally, what do you mean by "successive accesses based on the first setup"?
Burst mode.
1) Set Up Memory Address A to Read From
2) Read data at A
3) Read data at A + 1
4) Read data at A + 2
Internally DRAM is wider (e.g., 4096 bits) than the external bus width (e.g., 32 bits*). Think of DRAM as a 2D array of memory cells, e.g., 4096 rows x 4096 bits = 16mbit / 2MB. When you set the memory address to read from in a DRAM an entire row is selected, and from that a column is read. These are RAS and CAS (Row, Column Select). First setup sets up RAS and CAS.
Someone worked out that if you don't need to change RAS, you can read multiple columns by updating CAS only.
Then someone else worked out you could simply increment CAS internally to the RAM, and keep on pumping out the data in a burst. For SDRAM this burst length is 4 (I think). Newer memories have longer bursts. There are alignment issues too, you can't burst over the end of a row, and so forth.
This is a simple explanation, and I'm sure I've got things inaccurate and will be corrected!
* actually many DRAMS have 1-bit, 4-bit, 8-bit or 16-bit external buses, and you use multiple DRAMS in parallel to get the desired memory bus width.
