Minimig v1.1 ARM Hardfile Demonstration

[Illuwatar]

Clever idea by yaqube with the piggy backing. But he is not disabling the original 2 MB SRAM on the board - he adds an extra 2 MB (making up these 4 MB total). The CS1-pin (nr 6) are used to choose what half of the 2 MB that will be used. All other pins are connected in parallel - that is normal and should be like that. Even on a standard 2 MB MiniMig, all pins except of CS1 are connected in parallel. The core of the FPGA has been modified to provide four chip select signals instead of just two.

Someone complained about the amount of free space at my MiniMig design - here is a reason to fill it up... these mods will keep me busy changing the design all the time. I hope there will be a final so I can make the Ultimate Mini-ITX MiniMig. I would be nice to put that ARM thing right on the motherboard too...

[Illuwatar]

whiteb wrote: Are you sure ? The signal is a CS (Chip Select), its one OR the other. CS means one or the other, not both. And if the chips were to be used concurrently, they would need separate address lines. (Read, not enough I/O on the FPGA).

Whats stopping us from putting higher density with the same trick ?

Yes - I'm sure. That's the whole idea with Chip Select - to select what chip to read/write. Also, if you look at the pictures in the linked thread - the piggy backed parts are 512 x 16 (1 MB), so there is no way they alone makes up the total 4 MB. He needs the two other ones too. The two wires added to the FPGA spare ports are the new CS-signals, giving the design a total of four CS signals, one for each SRAM chip. Internally, inside the FPGA, there is an address decoder, converting the two most upper addresses (not seen externally) to these four CS signals (don't know the exact implementation, but two address lines gives you four CS).

Higher density = more address lines = more pins and different pin layout (needs a new PCB). The next step is 1024 x 16 (2 MB) SRAM and they don't fit (I use these on my Mini MiniMig to save space).