Welcome, Guest. Please login or register.

Author Topic: Hyperion/A-EON introduce us to the AmigaOne X1000. A new beginning?  (Read 74953 times)

Description:

0 Members and 1 Guest are viewing this topic.

Offline MskoDestny

  • Sr. Member
  • ****
  • Join Date: Oct 2004
  • Posts: 363
    • Show all replies
    • http://www.retrodev.com
Quote from: x303;536673
Looks very impressive.
I think this processor fits all the fancy X names: http://en.wikipedia.org/wiki/Xenon_%28processor%29
Hope they're gonna use something like it.

It's most certainly not that. It's a dual core processor conforming to Power Architecture 2.04. If Wikipedia is to believed the only processors conforming to that spec are the PA6T from PA Semi and the AMCC Titan. Xenon is only Power Architecture 2.03. Since PA Semi got bought by Apple, the Titan seems like the most likely candidate. I suppose something with the e500mc core in the QorIQ from Freescale woud technically fit the description too (it conforms to Power Architecture 2.06 which is a superset of 2.04).
 

Offline MskoDestny

  • Sr. Member
  • ****
  • Join Date: Oct 2004
  • Posts: 363
    • Show all replies
    • http://www.retrodev.com
Re: Hyperion/A-EON introduce us to the AmigaOne X1000. A new beginning?
« Reply #1 on: January 06, 2010, 03:53:04 PM »
Quote from: SamuraiCrow;536745
With a few custom interrupt handlers, anything interrupt driven will be accelerated by the new Xena chip.  The fact that it doesn't have to store its registers while processing those interrupts will make it preferred over other interrupt solutions.

I don't get the impression that it can handle interrupts on the main machine. It can handle changes to its I/O lines in an interrupt like fashion, but since all of its I/O lines are hooked up to the Xorro slot that presumably means that none are hooked up to the rest of the hardware on the board (which makes sense since the CPU is probably a SoC with most of the other harware like the ethernet, USB and PCIe controllers on the same chip). Presumably the connection between the XCore and the CPU is via the XCore's JTAG interface.

As a result, I doubt it will be useful for much without some kind of Xorro card unless you have some processing to offload that will fit in 64KB of RAM.
 

Offline MskoDestny

  • Sr. Member
  • ****
  • Join Date: Oct 2004
  • Posts: 363
    • Show all replies
    • http://www.retrodev.com
Re: Hyperion/A-EON introduce us to the AmigaOne X1000. A new beginning?
« Reply #2 on: January 07, 2010, 08:17:29 PM »
Quote from: arnljot;536965
Amiga is far behind, smp, memory protection, security model for multiuser, java, 3d, wifi, usb, firewire... The list could probably be longer kolla. But we need to start somewhere, or the gap will just grow.

One has to wonder whether it's worth trying to catch up vs starting with a more modern design. I imagine the number of existing Amiga apps that you would actually want to use these days other than hardware hitting games is pretty small. Amiga OS's ease of use was high for its day, but I'm not convinced its terribly remarkable these days.

The only real thing Amiga OS has going for it these days is that it's lightweight and relatively simple. However, you can get that without bringing along a bunch of design baggage intended to deal with the limitations of 80's technology (lack of memory protection for example). Apart from requiring expensive PowerPC hardware and running decade old software (if not older), what does Amiga OS bring to the table that something like Haiku or Syllable does not?
 

Offline MskoDestny

  • Sr. Member
  • ****
  • Join Date: Oct 2004
  • Posts: 363
    • Show all replies
    • http://www.retrodev.com
Re: Hyperion/A-EON introduce us to the AmigaOne X1000. A new beginning?
« Reply #3 on: January 08, 2010, 02:49:43 AM »
Quote from: SamuraiCrow;537011
I think the XCore chip on the X1000 is wired to the main memory bus in such a way that it can be a slave processor for replacing interrupts with.  The author of the Radeon drivers for OS 4 said as much on this amigaworld.net thread.  See post #21.

I don't think he said what you think he said. He said that essentially a hardware thread can wake up with very low latency in response to an I/O event essentially like an IRQ on a traditional CPU. Not that it was hooked up into the IRQ routing of the rest of the board. I don't see how it could be given that all the I/O lines are routed to the Xorro slot and the only other signals are power, a few control signals and JTAG.