C64 FPGA Idea

[trekiej]

I was wondering if some one thought about widening the bus for the 6510 processor.
Eight bit opcode and an eight bit or 16 bit operand for a fpga c64 sound interesting.

[trekiej]

I have heard of the 65C816 and have one.
Maybe some one could do a core for the MCC 216.

[trekiej]

I would like a chameleon too.
I am wondering if a wider buss is possible in the design.
I hear that the c64 has a 256 byte memory page.
It is suppose to be faster if one keeps code inside that page instead of trying to move
Address H and Address L all the time.

[trekiej]

My idea come from the layout of the pdp-1. It has an 18 bit instruction where it has a 12 bit operand.
If it could move a 16 bit operand in the same time as an instruction fetch, I do not doubt it could speed things up.

[trekiej]

SuperCPU, I do not believe they are still being made.

I guess it depends on if the Instruction Decode can be re-written to transparently handle it.
*******************
What you can do is :

Up the CPU clock rate.
Lower the instruction timings (fewer clock cycles per instruction).
Lower the RAM R/W timings (fewer clock cycles per read/write).
********************
These are fine by me too.

[trekiej]

The VGA version of the MCC-216 was demonstrated at the April SCCAN meeting when members Dan L. and Matt B. brought it in a surprise presentation (they also brought a Minimig to show off).

Next SCCAN meeting on June 5,
Robert Bernardo
Southern California Commodore & Amiga Network
http://www.sccaners.org
July 23-24 Commodore Vegas Expo v7 2011 - http://www.portcommodore.com/commvex

Is there anything new to post on the MCC-216 or sccan?