I completely agree with Billt. Yes, I work designing super large ASICs.
The RTL coding for an FPGA is really easy, the layout is a bit more tricky but not difficult.
However, you have to pay a lot of money for the tools and cell library - the basic building blocks optimised for the fab and process you are using.
The mask set costs for any modern process are HUGE. Then you have to design the place and route software which is many many person years of work.
I can get a modern FPGA on a 28n process for a few $ in volume, because the big boys split the development cost between zillions of customers.
Both Xilinx and Altera provide decent free software, so I would rather spend my time using start of the art devices than designing them in this case
/Mike