Vampire 600: FPGA A600 Accelerator Preorder

[majsta]

Hi
For example newest rumors on German forums is that design of accelerator is not mine. Also there are rumors that I don't use SDRAM on the board that I somehow fake everything. I don't know but when I waste my time reading what people are saying about this it is interesting to me that they still don't see that all of this is simple if you think outside of the box. If you try to connect your knowledge with this new approach you may end up talking technical stuff that make no sense anymore. Only few people in the world has the opportunity to see the board. Few days ago I went to Djole's office and talked about this project. He has seen Vampire 500 accelerator. One board left to UK to AMR and he is doing his own core for it. Soon we will have lot of people who are interested in developing their own cores based on my guidance not just using mine core. So what if all of this is fake? What if all of this is not stable or usable in any way? What if all of this does not exist? I think that this is last chance for classics amiga and if this goes down we won't have the time or ideas to think of new way where amiga should go. I think that FPGA has the answers for saving amiga. It is so powerfully.Magic!!!

[majsta]

Hi Don't get me wrong all of the negative comments are fine by me and i don't take anything regarding that too serious. People can thing and feel whatever they like

Regarding Vampire 500. Project is put on hold due to high interest for Vampire 600. At the moment where last testings were performed Vampire 500 had about 8Mips and 8 autoconfig mem(total 64MB) but I had some problems with IDe controller. Code for IDE controller is finished about 90% but didn't have the time to finish it. And Yes this boards will be produced also but it seems in much much larger quantities because demand is even higher than for Vampire 600.

[majsta]

@Mrs Beanbag
that is what is all about to many people participate in this and that we build new cores constantly and put them into board. So anyone with VHDL or Verilog knowledge can try and best thing is that you can't damage A600 or accelerator itself because there are lot of protection modules there.

About those accelerators for A1200, we will see...

[majsta]

Yes that's correct but I don't think that in the future adding such cache will be some huge problem. Also current cache can be improved so right now no one can calculate limits of this design.

[majsta]

@NovaCoder I was able to run it at 14.34Mips as I recall but it was not so stable. I left that code to wait until I get everything stable so I will back to that in matter of days to see what was wrong. I think that most of the problems was related to metastability and chip ram accesses and since i have solved that it shouldn't be such problem to get it working at higher Mips.

I have no idea how you create such wonderful ports but I would like to try something on my configuration, maybe then we could see real testings from this accelerator.