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Author Topic: Motorola 68060 FPGA replacement module (idea)  (Read 53024 times)

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Offline jkonstan

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Re: Motorola 68060 FPGA replacement module (idea)
« on: March 17, 2013, 07:33:31 PM »
Frederic,
your 68K core (Verilog) code looks interesting and appears to have taken a fair amount of effort. This is some good work.
How much validation have you done on your 68K Verilog CPU core?
The MC216 is the only place that this core is in use as the 68K core? The older Minimig code ports use the TG68K VHDL 68K core (Minimig DE1/DE2/MIST code ports).
I looked over the J1 Fourth CPU paper as well.  

Quote from: FrenchShark;729538
Hello,

I have done that already with the J68 core :
https://github.com/rkrajnc/minimig-de1/blob/master/minimig-src/j68/j68.v
It is loosely based on the J1 core (hence the name). So the heart of it is a stack-based CPU.
The ALU is a 16-bit ALU, compatible with a 68000 ALU.
It has some special micro-instruction for the effective address computation.
The core must run 2x to 3x faster than the original to reach the same speed.
The advantage is the size : less than 2000 LUTs. Micro-code take 2048 x 20 bits.
With further optimization (cache, prefetch, 32-bit ALU and effectve address ALU), I am sure it can be as fast as a 030/040.
Right now, this softcore can boot a Kickstart 2.04 in my AmiSOC core.

Regards,

Frederic
 

Offline jkonstan

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Re: Motorola 68060 FPGA replacement module (idea)
« Reply #1 on: March 18, 2013, 12:53:18 AM »
Fredric,
In your 68K Verilog code, I did not see code for the 68k interrupt acknowledge cycle (IACK cycle). The Amiga uses the 68K interrupt acknowledge cycle while the Atari ST (68K) uses both 68K Auto vector interrupts & 68K IACK cycle (for 68901MFP).
I may have missed this in your code, or do you need to still add this support in your 68K core?

Quote from: FrenchShark;729572
I was comparing the ways :
- Taking a picoblaze to emulate a 8051
- Taking a J1 to emulate a 68000.
I would not take a J68 just to make a keyboard controller. :-)

Moreover, emulation is not the exact term since the 68000 "emulation" is heavily HW assisted :
- instruction decoder generates microcode address
- specialized micro instructions help evaluating the effective address
- the ALU is 68000 compatible

On the J68, the bus interface is what is taking most of the room (1000+ LUTs).
Big endian is cool but really resource hungry.

Regards,

Frederic