Motorola 68060 FPGA replacement module (idea)

[Heiroglyph]

@wawrzon, Any application that has failed for you because of accelerators ?

For buses in general:
 * Latency
 * Capacity (Mbit/s)
 * Electrical compability
 * Protocoll conversion

So I think PCI is doable but don't forget that translation between PCI and Zorro may introduce bottlenecks. But why introduce any bus at all between the CPU-in-FPGA and the CPU-socket? KISS..

I don't think FPGA alone is up to the task.  I think you'd get a slightly faster 060 at best and it would cost more than it's worth.

My proposal was to connect a current CPU of some kind to the Amiga bus as directly as possible and emulate an 030.

The directly as possible part is the big catch. PCI(-e) pretty much dominates the market these days, there aren't really any other good fast interfaces to new CPUs and not even that on the really cheap nice SOCs, you have to go up a notch to even get PCI(-e).

[Heiroglyph]

why nobody?
http://www.powerphenix.com/ctpci/english/overview.htm

Ok, nobody on Amiga

[Bobo68]

Ok, nobody on Amiga

you'll try

[Bobo68]

Ok, nobody on Amiga

because there is m diator on amiga

[Heiroglyph]

you'll try

I'd rather get an SOC as the CPU, then you'd get a PCI bus and all other devices on the chip essentially for free.

[Heiroglyph]

because there is m diator on amiga

Don't get me started on their driver business model...I'd almost compete out of pure spite.

[wawrzon]

@wawrzon, Any application that has failed for you because of accelerators ?

none i remember or would seriously care for.

So I think PCI is doable but don't forget that translation between PCI and Zorro may introduce bottlenecks. But why introduce any bus at all between the CPU-in-FPGA and the CPU-socket? KISS..

i think we are talking to almost drop zorro or at least zorro3, and have a direct pci interface next to amiga being interfaced by pci as well. no zorro bottleneck between cpu and pci anymore. i understand the zorro pci interface would be used to interface the remaining amiga hardware or whats left of zorro bus.

[Bobo68]

I'd rather get an SOC as the CPU, then you'd get a PCI bus and all other devices on the chip essentially for free.

Show me the  SOC with 68K code

[wawrzon]

why nobody?
http://www.powerphenix.com/ctpci/english/overview.htm

if the designs are open could be used as reference.

[freqmax]

So what bus does the SoC of reasonable price, package and availability use?

[Heiroglyph]

none i remember or would seriously care for.

i think we are talking to almost drop zorro or at least zorro3, and have a direct pci interface next to amiga being interfaced by pci as well. no zorro bottleneck between cpu and pci anymore. i understand the zorro pci interface would be used to interface the remaining amiga hardware or whats left of zorro bus.

I'm just trying to replace the CPU slot connector/bus (the trapdoor or local slot on big box Amigas) with something that works with today's standards so we have the option to connect to something newer than the 060.

It would have no effect on or connect to ZorroII.

It might be smart to ignore or disable ZorroIII to simplify the design at the cost of the few cards that use it.

[Mrs Beanbag]

Forgive me if this sounds terribly stupid, but surely an Arm chip (for instance) has data and address buses that we could connect to the trapdoor slot via some relatively simple FPGA glue logic, just as we would a 68060?

[billt]

Forgive me if this sounds terribly stupid, but surely an Arm chip (for instance) has data and address buses that we could connect to the trapdoor slot via some relatively simple FPGA glue logic, just as we would a 68060?

You might look for one with an EBI bus. (I htink that's what it's called) forgot about that one until today. I'm not sure what kind of selection there is though, I'm only aware of moderate performance ones between 100MHz and 200MHz which don't thrill me for this task. But I don't know much about the higher-end ARM chips. This is typically used for memory, bu tmay work for this sort of project as well.

I'm not aware of any ARM chips that expose an AHB or APB bus externally for connecting to an FPGA, which would probably be preferable to EBI. The new ARM SoC FPGA chips DO (as I understand) expose the newer AXI system bus internally to the FPGA, which is part of my attraction to them. Cool stuff! Yes, somewhat to terribly expensive just now, but I've only found the Xilinx low and high end ones at Digikey, I haven't found the Altera ones anywhere to compare. Maybe they aren't quite out the door just yet. I'm hopeful that prices will adjust when both companies have them on distributor shelves.

[Bobo68]

Forgive me if this sounds terribly stupid, but surely an Arm chip (for instance) has data and address buses that we could connect to the trapdoor slot via some relatively simple FPGA glue logic, just as we would a 68060?

I think the logic won't be so simple as we want.
because 020 and 060 buses so close each other

[Heiroglyph]

You might look for one with an EBI bus. (I htink that's what it's called) forgot about that one until today. I'm not sure what kind of selection there is though, I'm only aware of moderate performance ones between 100MHz and 200MHz which don't thrill me for this task. But I don't know much about the higher-end ARM chips.

Finding one that has that plus external interrupts with levels is tricky.

It's also not standardized across chips so you're back to vendor lock-in.

[freqmax]

Interrupts can be handled by letting the Amiga side setting an interrupt register in the FPGA which in turn just signal a general interrupt (like "IRQ" on C64) to the overdrive CPU. The CPU side then reads what interrupt source that triggered the event and act accordingly. The extra performance will negate any delays for this code.

On 8086 etc.. an instruction may take 3 cycles but an IRQ may take 100 cycles just to hint on the amount of wasted cycles that may occur. Not counting Push/Pop instructions.