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Author Topic: Zorro II config pin on A500 expansion slot  (Read 438 times)

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Offline kamigaTopic starter

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Zorro II config pin on A500 expansion slot
« on: August 12, 2022, 03:30:53 PM »
I'm currently reverse engineering one of the PALs on a DataFlyer Plus card on an Amiga 500. One high-level goal is to create a list of PAL equations to program a GAL to duplicate the functionality. These PALs are dying in the field, and I'd love to enable people to fix their broken cards.

Does the CONFIG pin 11 on the Amiga 500 86-pin card edge get asserted low once the write to the $E8 0024 base address register happens? Is it the next amiga clock cycle? What pin/chip/device on the A500 is driving that signal? Is the expansion rom code that drives this process available?

I have an early first pass GAL I've created, but I'm not seeing that CONFIG pin drop. I want to make sure this isn't something that the PAL needs to output.... to ensure that CONFIG is an Amiga OUTPUT.

From the first memory read access cycle to the card, I'm seeing multiple ROM reads, which the PAL is handling the ROM Chip Enable properly, best I can tell. I see the incoming latch write, and latch the newly configured ($E9 xxxx) address from the Amiga data bus. What I'm not seeing in comparison to a working PAL, is that ~200ns after the latch enable, CONFIG drops which tells the 8-bit comparator to look for accesses at the new $E9 space.

What's the best documentations source for this?

Thanks