For randomly accessing memory your speed is 266Mhz / 16 = 16.625Mhz which is the same speed as the memory u already have on your Amiga accelerator card.
I think the latencies are based on the io bus clock, not the memory clock. So it's not 266/16, it's 1066/16. The reasons why the latencies get higher is because of the increasing gap between the two clocks. The computer is using the io bus clock, so it makes sense for it to be based on that.
Old ram from the 90's also has page setup times. Fast page mode and static column were equivalent to how memory is accessed now, if you were accessing data in different pages then you had the latency. Because of this the 030/040/060 can burst reads from ram a cache line at a time.
http://en.wikipedia.org/wiki/Dynamic_random-access_memory#Fast_page_mode_DRAM_.28FPM_DRAM.29 Ram is wider now than it was, so if you were creating a 68k memory controller with DDR3 then you'd keep reading the entire page from the ram all the time there was no other memory access required. You've paid for the entire page to be read, it just needs to be transferred and that bus can run up to 1066mhz. Even if the code does random access memory often, which would make you want to stop caching other data, the page is more likely to still be open compared to old 90's memory as it's bigger (like 256 bytes).
http://en.wikipedia.org/wiki/Prefetch_buffer Suggesting that modern ram is the same speed as old ram is wildly missing the point. It's a lot more complex to interface to, but if you could hook up ddr3 to a 68060 then it would run quicker.