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Author Topic: Intel parries K8? New new memory technology.  (Read 1207 times)

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Offline FloidTopic starter

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Intel parries K8? New new memory technology.
« on: April 07, 2004, 01:06:07 AM »
FB-DIMMs might be the next other big thing.  See TheInquirer article.

So on the one hand we have K8 with low latency and relatively low complexity for boardmakers in every domain but memory... while Intel solutions are, in comparison, blocks of Intel property that must be laid out just-so, but this new toy dramatically simplifies the DIMM-bank dillemas... and paves way for the terabyte banks the big databaseniks are droolink for.  AMD will doubtless pull some hairs over whether to license(?) and implement this or carry on as-is; IBM, Apple and friends will have to ask similar questions.  There's still some time before the issue gets forced.

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Suggested listening, in light of this and today's other news: the Dub Narcotic Sound System's F*** S*** Up.

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Edit:  Looks like Dell is sitting pretty, of course.
 

Offline FloidTopic starter

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Re: Intel parries K8? New new memory technology.
« Reply #1 on: April 07, 2004, 09:54:38 AM »
Wow, this sure got a whopping 7 reads.  TheInq has one more update, and with IBM on the JEDEC panel (and Intel-the-technology-company happy to play through JEDEC in ways Rambus-the-'IP'-company wasn't), it sounds like no one will be left in the technological cold.

Whether this makes the K8's memory controller a high-performance detour or a heralding of things to come... (This topology smells not entirely unlike HT, and if you can 1. standardize the interface for a longer lifetime than was had with DDR while 2. handling trace lengths that easily place the DIMMs wherever's thermally and physically convenient and 3. possibly even save pin count, it's hard to see why you'd bother putting a controller anywhere but on-die*) ... It'll be interesting to find out.

It's almost a shame things could work out royalty-free, because I've been itching to see if 'pure' HT could be pressed into service toward the same end... even if extra bridge chips might thus be required.  This is SCSI- or IDE- for RAM in the best case, but AGP in the worst.  (The reliability features and purposed-design_vs._latency are sugar, and it's not clear how kludgey it'd get to implement a 'pure' memory bridge with HT, but if 'smart' RAM is the future -- as 'smart' GPUs were in the early '90s -- then we might be getting yet another bus more equal than others.  Back to the flip side, speed is king, and Motorola wouldn't have picked Firewire over MPX just because it was more standard.** :-P)

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Now, uh, all 5 or 6 or you can see why I didn't want to jump the gun and post this as news.

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*As far as I can tell, NUMA still gives you an excuse for N times more parallelism in terms of banks, and/or throws in entire extra CPUs 'for free' as you scale.  Meanwhile, if you're memory-constrained and have the cash to consider things like racks of DIMMs, that extra firepower might just mean extra cost on your power bill... and Intel's just spun a 180 into the "Cool Computing" camp.

**Or AMD wouldn't have picked RS-232 over EV7, or IBM wouldn't have picked USB over the 970's 'elastic bus,' but I'm straining for a neutral analogy.