Questions about Minimig future

[nBit7]

LVDS and CML 3.3v (DVI/HDMI) at the physical level don't look the same to me.

As I said before the physical voltage levels are not that important. Its the difference in voltage between the complementary pair that decides if it is a logic 1 or 0.
However the voltages must remain in the common mode window of the receiver.  LVDS normally terminated by 100 ohms generates at least 200mV differential at the receiver which is more than the 150mV receive window shown in the DVI spec.

[freqmax]

@nBit7:
You think it should work?, if not what would be needed to make it work do you think?

[nBit7]

freqmax wrote:
@nBit7:
You think it should work?, if not what would be needed to make it work do you think?

I think that LVDS (current mode) drivers terminated to Vcc by 50 Ohms is a problem.  If you have access to the termination then you should be able to get it working.  Otherwise it may be possible to have a passive network that would allow it to work but it would likely have a drastic affect on max cable lengths.  You would probably also need to have a floating (offset) GND reference on the LVDS side.  I would have to do a more complete analysis of the LVDS drive circuitry to say anything with any level of assurance.

[nBit7]

This App note suggests that it is possible (LVDS to CML) by using AC coupling.  The protocol of DVI/HDMI should make AC coupling possible.

http://pdfserv.maxim-ic.com/en/an/hfan10v2.pdf

[alexh]

nBit7 wrote:
This App note suggests that it is possible (LVDS to CML) by using AC coupling.

If I actually knew what that was I might be able to comment, I need to learn Analog. It's all "magic" AFAIC