Did you see
this picture?
I would guess that with no FPU oscillator installed that the FPU is synchronous with the CPU. JP1 probably controls whether to use the CPU crystal or FPU crystal.
JP2 is probably a compatibility kludge for RAM above or below a certain ns rating.
And I'd guess JP3 enables or disables either the SCSI controller or the entire board.
Only guesses - maybe someone knows for certain.
