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AuthorTopic: My idea for a new computer: Part 1 inside the case  (Read 3736 times)

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Offline Kalvan

My idea for a new computer: Part 1 inside the case
« on: December 22, 2011, 06:01:49 PM »
Hibana Computers Series 1:
 
CPU: Custom 1-8 core design based on the MIPS Prodigy Core IP; Includes full main MIPS 32 and MIPS 64 CPU Instruction Sets, plus MIPS Concurrent instuction extensions. As Each core is capable of four threads each with 4 64 bit integer or 96 bit floating point instructions (aside from long division, and a few other corner cases) every clock cycle, that means 40,000 MIPS Per Core@2.5 GHz on Global Foundries 28nm High Performance Process
 
General Purpose DSP: Texas Instruments 2-8 Core 32C0XX DSP or recent vintage, binary backward compatible with almost all previous mainstream TI DSPs.
 
System RAM: Micron Technlolgies RLD3 DRAM of variable quantities (But no less than 4 GB) and variable speed (But no less than 1600 Mhz)
 
GPU: Custom Design created by stitching together a 16 Core Imagination Technologies PowerVR GPU to 2048 Adapteva Epiphany 64 bit Cores via the AMD/ARM Front Side Bus Architecture. Should be good for 4.5 Double Precision TeraFLOPS, and roughly 80 Gigatexels/Second@750Mhz. Optional Caustic Graphics Raytracing Co-Processor on high end models. Total Power Draw no higher than 36 watts (without overclocking). Connected to 2GB of either RLD3, XDR2, or GDDR5+ DRAM as a framebuffer. Support for up to 2560x1600 Resolution. Full Support for latest versions of OpenGL, Open CL, and OpenRL in the driver stack, as well as methods for access of hardware at lower levels.
 
Sound System:
Sound CPU: Custom 2 core Renesas SH5-DSP @1Ghz
Sound Synthesis: AMY PCM and Additive Synthesizer. 64 Channels of Additive Synthesis@192Khz sampling rate. (If CommodoreUSA Runs with it, it can be replaced with a PAULA simmilarly enhanced,)
 
Network Adapter: Cutomized Bigfoot Networks Killer E 2100 with ARM Level 7 Controller @ 800 Mhz and 1024MB DDR2 Network Buffer
 
BUS Controller:
OSCAR Custom Bus Hub Based on four cores Freescale Coldfire Level 5 or Natami 68050 core@ 1.5 Ghz
 
North Bridge: Lucid Logix HYDRA 300 North Bus Generating at least 48 lanes of PCI-Express 3.0, supporting 2x16, and 2x4 motherboard PCI-E 3.0 Slots @full bandwidth, and 1 PCI-E X16 2.1 slot @ full bandwidth.
 
Other Bus Chips: Miscelaneous Texas Instruments, Renesas, and IBM controllers for USB 3.0, SAS, and FiberChannel.
 
Special Coprocessors:
2 Anchronix Speedster 22i FPGAs. One with ca.5,500,000 ASIC Gates@1.5 Ghz, and One with ca. 25,000,000 ASIC Gates@750Mhz .
« Last Edit: December 24, 2011, 02:40:23 PM by Kalvan »
 

Offline Kalvan

My idea for a new computer: The Case and Peripherals
« Reply #1 on: December 22, 2011, 06:15:03 PM »
Local Storage:
 
Low End Desktop Systems will feature an OCZ Octane as a System Drive, and a generic 1TB SAS Hard Drive for Application and Data.
 
Mid Range Systems will feature the OCZ Ibis as a system drive, and seperate (sets of) 1TB SAS Hard Drives for Application and Data, respectively, in RAID 1.
 
High End Systems will Feature a customer's customized configuration of the OCZ RevoDrive 3 (or 3x2) for the System Drive, the Western Digital Velociraptor 15k or Seagate Cheetah 15k SAS Hard Drive for the Application Drive (RAID 0, 1, or 10 further optional) and Generic 2GB SAS hard drives in RAID 1 or 10.
 
Removable Storage:
 
For the Optical drive, I will shop around between Lite-On, Plextor, and Samsung as to who has the best bargain for Blu-Ray+DVD+CD Read-Write-Rewritable Drives with suficient bandwidth to stream 1080p in real time.
 
Flash Cards are another matter. Transfer rates for most card readers never reach USB 2.0 speeds, let alone SAS or SATA 2.0. I plan to start working with Rosewill, Sabrent, and NEC to develop SAS 3.0 (6 Gb/sec) card readers in all 4 regular formats, plus the new CFX Format.
 
Keyboard: choice between the Roccat Valo the Logitech G510, the Corsair Vengeance K90, and the Razer Star Wars: The Old Republic keyboard. In all cases, the Windows key will be replaced with a 花 key meaning "Hibana," and I may have Razer take away the Basic Letters on the Key. In addition (I'm not sure which), Enthusiast and Workstation models also add in the Razer Nostromo.
 
Mouse: Cyborg MMO 7, plus, depending on the computer model, a Space Mouse model from 3d Connexion
 
Case:
 
Entry-level systems will use the Silverstone Lascala Series of upright cases
 
Home Theater systems will use the Silverstone Crown series
 
Lower-Mid-Level systems will use the Fortress FT-03
 
Mid-Level Systems will use the Fortress FT-02
 
Enthusiast Systems will use the Raven RV-03
 
The Hypothetical Workstation and Server systems will use either the Silverstone Temujin TJ-11 or else a http://www.lian-li.com/v2/en/product/product06.php?pr_index=572&cl_index=1&sc_index=25&ss_index=138]Lian Li PCP80N[/URL]
« Last Edit: December 22, 2011, 06:17:27 PM by Kalvan »
 

Offline Kalvan

My idea for a new computer: Part 3 the opperating system/API/GUI
« Reply #2 on: December 22, 2011, 06:21:13 PM »
The Hibana Series 1's operating system will a UNIX-Alike. It will feature a kernel based on a chimera of OpenBSD, NetBSD, and Haiku, as rewritten in either a purely compiled dialect of Scala shorn of all Java Virtual Machine overhead, or else D. The Userland will be based on MicroXwin.
 
The GUI will combine the best, most useful aspects Xfce, Compiz, and KWin. The Command Line Shell will be a hybrid of FISH and Z Shell, as rewritten in Scala or D, and will also include a fully functional interpreter/compiler for that language. I will also include a full systhesis toolkit for the FPGAs.
 
As stated before, the graphics stack will fully support the latest specifications of OpenGL, OpenCL, and OpenRL, as well as custom APIs to allow lower level programming on the hardware. Also, while I will not support OpenACC in the first version of the OS (mostly because I am certain that NVidia is enguaging in Orwellian Doublespeak), I will, through Lucid's Hydra architecture, be offering a Multi-GPU solution that involves harnessing the GPUs (theoretically) more effeciently than Crossfire or SLI, and which can thereby be used in conjunction with the standard GPU too. Of course, this is contingent upon the Hibana OS Versions of ForceWare, QuadroDrive, Catalyst, and FireFuel not self-disabling themselves or trying to bypass their competitors's products or the standard GPU on the board after performing a system detection.
 
The Sound Stack will, as said before, include a direct hardware channel to the sound processor, and also the PCI-Express slots. Creative Labs, ASUS, Turtle Beach, or anyone else who thinks that they can make a better sound processor chipset and do it honestly is welcome to try.
 
The Kernel itself shall be written so that any of the other general purpose processors (specifically, the TI DSP, the Sound CPU, OSCAR, or the ARM control processor in the NIC) can be sent properly flagged code straight to them, or any of them can even be temporarily be designated the CPU. I'm doing this because I wanted to design a computer that, among other things, would be an arcade game emulator writer's paradise system. All major Arcade CPU families except for Intel, Zilog, and MOS Technology are included and at speeds that way excede the originals (Motorola 680X0 through OSCAR, Motorla 680X/Hitachi 6309/H8/SuperH through the Sound CPU, ARM through the NIC Controller, TI 320CX0 [Used by Atari and Midway-Williams] and of course MIPS). And for any chips left out, the FPGAs are more than large enough to soft code for them.
 
Finally, the file system will be based on a fully integrated fully functional database system, so that when it's time to go upmarket, I will be able to do so with minimal hiccups.
 
Questions? Comments? Flames?
 

Offline Middleman

Re: My idea for a new computer: Part 1 inside the case
« Reply #3 on: December 23, 2011, 03:41:45 AM »
Hi Kalvan,
 
Interesting concept you got there. Are you familiar with making electronic boards yourself. Have you talked with anyone else about this including how much it would potentially cost to make?
 
I'm not an expert on this sort of subject, but would be interested to see what comes of it, like FPGA Project has done > www.fpgaarcade.com
 

Offline Bif

Re: My idea for a new computer: Part 1 inside the case
« Reply #4 on: December 23, 2011, 04:43:21 AM »
Quote from: Kalvan;672406
Hibana Computers Series 1:
 
CPU: Custom 1-8 core design based on the MIPS Prodigy Core IP; Includes full main MIPS 32 and MIPS 64 CPU Instruction Sets, plus MIPS Parallel instuction extensions. As Each core is capable of four threads each with 4 64 bit integer or 96 bit floating point instructions (aside from long division, and a few other corner cases) every clock cycle, that means 40,000 MIPS Per Core@2.5 GHz on Global Foundries 28nm High Performance Process
 


Did you get the 40,000 MIPS per core from MIPS? Because if you are calculating it by yourself I think you may be making a gross error. Hardware threads do not equal CPU cores (that's why they are threads, not cores). Each thread will have its own set of registers but otherwise typically has to share most of the other functions of the processor (like integer and floating point units). So only one thread at a time can be running an FPU computation per cycle. So your MIPS is more like 10,000 per core.

The main reason CPUs started offering HW threads is to mask increasingly long memory latencies as memory hasn't kept up with CPU speed. While one thread is waiting 500 clock cycles on a load dependency, one of the other threads can be using the FPU if they have finished loaded their data. So HW threads are just there to get better utilization of the existing CPU, not multiply performance linearly.

I would be really surprised if MIPS or anyone has some magical core that will dust X64 without costing heaps more.

Anyway, this was a fun read but mostly because it's fairly ludicrous on all sorts of levels to build something like this and expect people to buy it by the time you are done. Don't let me stop you from trying though :).
 

Offline Kalvan

Re: My idea for a new computer: Part 1 inside the case
« Reply #5 on: December 26, 2011, 03:18:47 PM »
Quote from: Middleman;672495
Hi Kalvan,
 
Interesting concept you got there. Are you familiar with making electronic boards yourself. Have you talked with anyone else about this including how much it would potentially cost to make?
 
I'm not an expert on this sort of subject, but would be interested to see what comes of it, like FPGA Project has done > www.fpgaarcade.com

All I need is US $100,000,000.00. $25,000,000 for the chipset and motherboard parts R&D, $25,000,000 for wafer space at Global Foundries, $25,000,000 for licenses, the venders, and to assemble the thing into computer systems (maybe less if I can negotiate wholesale prices), and $25,000,000 for OS development (including new compiler(s) for the development language(s), and hours and hours of bug testing), and Bob's your uncle.
 
Of course, that only gets you the systen in mass quantities. There's still the matter of distribution, advertisement, ongoing OS support, development systems to earlybird software developer candidates (Which will include the likes of Corel, Kaspersky, Id Software) and of course review hardware to major magazines and websites.
 
Like I said, this is probably going to be a project for when I get all six numbers and the Power Ball when the grand prize tops $300,000,000.
 
Oh, and I've finally found the maker of my laptop keyboards above the size of Netbook, Here. If Mr. Lebedev and company would be willing to do a wider version like the Optimus Maximus' layout, but using the Optimus Populares style of key for the Desktop Replacement/Portable Workstation laptop model, I would be most grateful.
 

Offline Kalvan

Re: My idea for a new computer: Part 1 inside the case
« Reply #6 on: December 26, 2011, 03:36:41 PM »
Quote from: Bif;672502
Did you get the 40,000 MIPS per core from MIPS? Because if you are calculating it by yourself I think you may be making a gross error. Hardware threads do not equal CPU cores (that's why they are threads, not cores). Each thread will have its own set of registers but otherwise typically has to share most of the other functions of the processor (like integer and floating point units). So only one thread at a time can be running an FPU computation per cycle. So your MIPS is more like 10,000 per core.

Well, according to a graphic in the press release on their website, they explicity state, using different colored blocks to symbolize instructions and threads, four threads X Four instructions per clock per threads = 16 instructions per clock per core.  With an asterisk and fine print on the bottom involving long division, vector math, and multi-register load and store opperations to different threads.
 
Quote from: Bif;672502
I would be really surprised if MIPS or anyone has some magical core that will dust X64 without costing heaps more.

That's the funny thing about those press releases on the website; they explain that all this computational power is due to a combination of "radically new cache technology" and massively out-of-order execution, but don't actually go into detail about the former.  Neither do they talk about prices per core or power consumption, except to say that the latter is "suprisingly small."  But if it's above $100.00 per core, then they've just shot my business model to heck.
 
Quote from: Bif;672502
Anyway, this was a fun read but mostly because it's fairly ludicrous on all sorts of levels to build something like this and expect people to buy it by the time you are done. Don't let me stop you from trying though :).

Thank you.  Glad you're having a good time.
 

Offline Tripitaka

Re: My idea for a new computer: Part 1 inside the case
« Reply #7 on: January 02, 2012, 10:26:55 PM »
Not sure about the choice of mouse, I prefer these ones:

http://www.gamingmouse.co.uk/gaming/r2-omnimouse/

It all depends if your a hand or fingertip kind of user I guess (f 'nar).
Falling into a dark and red rage.
 

Offline Kalvan

Here's a hardware update:
« Reply #8 on: April 11, 2012, 09:16:32 PM »
CPU: Custom 1-8 core design based on the MIPS Prodigy Core IP; Includes full main MIPS 32 and MIPS 64 CPU Instruction Sets, plus MIPS Concurrent instuction extensions. As Each core is capable of four threads each with 4 64 bit integer or 96 bit floating point instructions (aside from long division, and a few other corner cases) every clock cycle, that means 40,000 MIPS Per Core@2.5 GHz on Global Foundries 28nm High Performance Process
 
General Purpose DSP: Texas Instruments 2-8 Core 32C0XX DSP of recent vintage, binary backward compatible with almost all previous mainstream TI DSPs.
 
System RAM: Micron Technlolgies RLD3 DRAM of variable quantities (But no less than 4 GB) and variable speed (But no less than 1600 Mhz)
 
GPU: Custom Design created by stitching together a 16 Core Imagination Technologies PowerVR GPU* to 2048 Adapteva Epiphany 64 bit Cores via the AMD/ARM Front Side Bus Architecture. Should be good for 4.5 Double Precision TeraFLOPS, and roughly 80 Gigatexels/Second@750Mhz. Optional Caustic Graphics Raytracing Co-Processor on high end models. Total Power Draw no higher than 36 watts (without overclocking). Connected to 2GB of either RLD3, XDR2, or GDDR5+ DRAM as a framebuffer. Support for up to 2560x1600 Resolution. Full Support for latest versions of OpenGL, Open CL, and OpenRL in the driver stack, as well as methods for access of hardware at lower levels.
 
Sound System:
Sound CPU: Custom 2 core Renesas SH5-DSP @1Ghz
Sound Synthesis: AMY PCM and Additive Synthesizer. 64 Channels of Additive Synthesis@192Khz sampling rate. (If CommodoreUSA Runs with it, it can be replaced with a PAULA simmilarly enhanced,)
 
Network Adapter: Cutomized Bigfoot Networks Killer E 2100 with Qualcomm Snapdragon S4@ 1.5 Ghz+ and 1024MB DDR2 Network Buffer
 
BUS Controller:
OSCAR Custom Bus Hub Based on four cores Freescale Coldfire Level 5 or Apollo ASIC@ 1.5 Ghz
 
North Bridge: Lucid Logix HYDRA 300 North Bus Generating at least 48 lanes of PCI-Express 3.0, supporting 2x16, and 2x4 motherboard PCI-E 3.0 Slots @full bandwidth, and 1 PCI-E X16 2.1 slot @ full bandwidth.
 
Other Bus Chips: Miscelaneous Texas Instruments, Renesas, and IBM controllers for USB 3.0, SAS, and FiberChannel.
 
Special Coprocessors:
2 Anchronix Speedster 22i FPGAs. One with ca.5,500,000 ASIC Gates@1.5 Ghz, and One with ca. 25,000,000 ASIC Gates@750Mhz .
 
*Preliminary models will use the SGX 554, Subsequent models will use the 6 Series "Rogue" core.
« Last Edit: April 17, 2012, 01:55:36 PM by Kalvan »