Yes, you can divide by 3 but your resulting clock still may not be a proper E clock because of the 60/40 duty cycle. So you would be better off with logic counting 10 (7 MHz) clocks and creating the proper duty cycle. You don't need to worry about VPA timing but the VMA timing may need some wait states or at least latching with the 7 MHz clock.
Also, you need logic (often described as 68000 state machine logic) to guarantee at least one 7 MHz wait state on the 68000 Address Strobe, Dtack sampling on the third 7 MHz clock and cycle termination on the falling edge of the last 7 MHz clock. The reason I am warning you about Dtack sampling on the third 7 MHz clock is because Commodore allowed sloppy Zorro2 designs with early Dtack generation. Note: The Upper and Lower Data strobes may or may not need to be delayed on write cycles.
Now, just in case that's not enough to consider, the 68000 state machine logic needs to handle the bus arbitration signals with the proper 7 MHz timing too! 
Great info shared… Thanks 🙏🏻
