Motorola 68060 FPGA replacement module (idea)

[Mrs Beanbag]

I suspect the biggest speed boost would come from full pipelining. I would guess the RAM could be fast enough relative to the FPGA for a data cache not to be that important, but an instruction cache might help. There are pipelined FPGA cores, MIPS of course being a prime example.

A RISC core with 680x0 programming model should be fairly easy, starting from for instance a MIPS core, then add a microcode engine. I mean if you know what you're doing. Which I don't, sadly.

[Mrs Beanbag]

I forgot about RAM latency, but wouldn't RAM at 1333MHz and CL9 still be able to max out a 100MHz CPU?

Would there be any advantage to using graphics memory in this application? (i.e. GDDR4/5 rather than DDR2/3)

[Mrs Beanbag]

then your speed drops like a rock

Confusing metaphor :crazy: When you drop a rock, it just goes faster and faster!

Ok, well, I'll take your word for it. So even an implementation of a plain 68000 would need some sort of cache in this case.

[Mrs Beanbag]

You know what I don't even care about 1333MHz RAM anymore, you can buy 8Mb chips of 16-bit SRAM:
http://uk.farnell.com/renesas/r1wv6416rbg-5si/sram-64mbit-3v-55ns-48fbga/dp/2068172
I guess that would be fast enough for an off-chip cache for an FPGA 68060 implementation, if not big enough for the main ram itself.

Maybe he will shoot this down for some other reason... but if I throw enough ideas at the wall maybe one of them will stick. Like a rock.

[Mrs Beanbag]

So in principle, if we were to use SRAM as memory, and FPGA as CPU at 100-ish MHz, would we still need a cache in the CPU core?

[Mrs Beanbag]

I will admit an instruction cache; it can be simpler because you don't write to it. Also even a plain 68020 has an instruction cache (albeit a small one).

Just trying to think in terms of "maximum impact/minimum effort". I'm thinking essentially 68020, but fully pipelined and fastest possible clock speed.

[Mrs Beanbag]

I see the problem with random access now... put simply, you have to read or write a whole block of data whether you want it all or not.

Just looking at the price of FPGAs. Can get a 550MHz Virtex 5 for just under £100, not bad. And it has >200k of block RAM!

Now I only have to learn VHDL...

[Mrs Beanbag]

It is this LX one:
http://uk.farnell.com/jsp/displayProduct.jsp?sku=1876187&CMP=e-2072-00001000&gross_price=true
Others in the range seem a lot more expensive.

True I wouldn't want to try soldering one. Maybe you can buy sockets.

[Mrs Beanbag]

Because X86 is much faster.

+more expensive
+more power hungry
+...

+ THE ENEMY

[Mrs Beanbag]

THEY ARE MORE POWERFUL

- who cares?

Seriously. If we only cared about raw CPU power, why do we care about Amigas at all? Because they have some charm that other computers don't. x86 has performance, but it has no charm. Ask yourself which you would rather go for dinner with.

Besides, hulking great desktop PCs with beastly CPUs are becoming something of a niche market these days. Most people seem to prefer the convenience of laptops and tablets, and if they want games too they get an Xbox. Only hardcore gamers need the performance of their x86-based PCs.

ARM is taking over, get used to it. x86 is the past of computing, not the future, and ARM will catch up with x86 performance before too long as well. Microsoft went to the effort of making Windows 8 work on ARM for good reason, they know the change is coming.

[Mrs Beanbag]

This is all an interesting idea. I don't know what the state of available FPGA cores for 68040 are, but a cursory search did turn up a Coldfire core. Might another option be to use a Coldfire FPGA core and modify the microcode of it to get around the incompatibilities. Weren't there just a handful of unimplemented instructions and a couple of instructions that behaved differently?

It might be a good starting point. Differences are:

1. No DBcc
2. No bitwise rotation (rol, ror)
3. No bitfield operations
4. Multiply instructions don't set flags. From the Coldfire manual:
CCR[V] is always cleared by MULS/U, unlike the 68K family processors

Coldfire also has a few extra commands (some of which would be quite useful, such as saturate and multiply-accumulate)

[Mrs Beanbag]

Maybe someone can find this useful:
http://www.oracle.com/technetwork/systems/opensparc/index.html
Obviously that is a different ISA altogether but such things as pipelining, cache etc are presumably ripe for the picking. I don't know very much about the Sparc ISA.

[Mrs Beanbag]

supposing one does a movem.w (SP)+,D0-D7 for instance... urgh

[Mrs Beanbag]

dunno I did just tweet a link to it so maybe it's my fault

some people will just hack anything though just because they can

[Mrs Beanbag]

the site seems to be back online now.