FPGAARCADE minimig compatible board, comments?

[jkonstan]

Mike,

Please post a pdf of the schematics so that we can give some better "design review" like feedback. Also, add an IDE connector via Spartan3e/level shifters (CBT16245).

 :-)

[jkonstan]

Mike,

The new TI spread spectrum Clock Synthesizers are nice parts as well.
 
http://focus.ti.com/docs/prod/folders/print/cdce937.html

I have seen a Spartan3 FPGA used for DDR controller where DDR clock generation was done via FPGA DLL, and it worked fairly well.

Are you going to use Hyeprlynx or another Signal Integrity tool to simulate your pcb layout ?

When you post the schematics, I will look them over.

 :-)

[jkonstan]

Simulate the pcb layout in Hyperlynx, and you will be ok.
The last Spartan3 that I simulated with DDR was only a point to point application, and the only termination resistor required was for DDR_CLK+/-. The rest of the I/O terminations for the interface were tweaked by controlling the Spartan3 pin drivers in the (Xilinx ISE .UCF file). If you use a Spartan3A instead of a Spartan3, you will have to add more external termination resistors because the Spartan3A I/O drivers do not have as much termination/impedance control as the Spartan3 does. Also, there are a lot of good DDR app notes from TI, Freescale, Xilinx etc.. as well.

 :-)

[jkonstan]

Mike,

I did not see the termination resistor (@ 100 ohm depending upon the actual Zdiff of Mem_CLK_P & Mem_CLK_N) across the DDR diff pair of Mem_CLK_P & Mem_CLK_N. This termination resistor should be placed near U6, the DDR IC (TSOP66).

  :-)

[jkonstan]

DDR takes a bit more simulation work than SDRAM; however, the memory bandwidth performance boost vs SDRAM is worth the effort if you have access to a SI simulation tool such as Hyperlynx.


 :-)

[jkonstan]

DDR pcb layout is more than just reflections & crosstalk.
DDR pcb has to be impedance controlled, and you have to have a range/window of trace length matching for different group of DDR I/O in order to meet timing requirements of DDR.
 :-)

[jkonstan]

Mike,

Most DDR designs that I have worked on or have seen had used had a @ 100ohm termination resistor across the DDR_CLK+/DDR_CLK- nets even when there was a termination supply and resistors to VTT(1.25V). Micron does call the DDR_CLK+/DDR_CLK- nets a differential clock (See Micron Technical note TN-46-14: Hardware Tips for Point-to-Point System Design).
 
DDR is a little more flexible with respect to trace length mathcing.

Here are the generic DDR_SDRAM net rules that I typically use:
------------------------------------------------------------------------------------------
 1. The DDR net groups (databyte0, databyte1, and Address/control) should be within 100mils of each other in length.
 2. All DDR nets should be within 500mils of each other in length.
 3. The DDR_CLK+/- should be within 20mils of each other in length.
 4. The DDR_CLK+/- should have @ Zdiff=100ohms+/-10ohms.
 5. Target Impedance for DDR nets should be in range 40 to 50 ohms.
 6. The DDR Data nets & DQMx for DATABYTEx in relation to data Strobe DQSx should be within plus/minus 35 mils in length.

Cost reduced DDR termination (short trace lengths and only a couple DDR ICs) would would genrally consist of series termination on DDR nets, a @ 100ohm termination resistor across the DDR_CLK+/DDR_CLK- nets, and VREF (1.25V) generation via resistor divider (1K/1K) of 2.5V DDR supply with a small .01uf cap for each Vref pin for each DDR IC. In Cost reduced DDR termination scheme, the National LM2995 VTT (1.25V)termination supply can be eliminated along with all of the resistors to VTT.

As long as you run simulations in Hyperlynx, you will be fine.

 :-)

[jkonstan]

Mike,

an extra set of 0402 or 0603 pcb pads & a resistor are very inexpensive; thus, I always include the pcb pads for a termination resistor across the DDR_CLK+/DDR_CLK- nets.

  :-)

[jkonstan]

Mike,

After looking at your updated schematic, the updated design looks pretty good to me. The only thing that I might have done differently is the power supply design because using a fixed 5V input power supply can lead to a fried pcb if someone uses the wrong power adapter (wall wart). At a Xilinx training seminar that I attended last year, our instructor fried a brand new Spartan3A DSP evaluation board by using the wrong power adapter (used a 12V power adapter instead of the required +5V power adapter).

Thus, you should populate zener D9 and R121 polyfuse and depopulate R120 for protection against this occurance since these populated pcbs are likely to cost a fair amount.
Since Dc to DC switchers were used, your other option would have been to just design the switchers with a wider DC input voltage range (5v to 19v) and add a +5V output switcher to the design.
 

Keep up the good work and keep us posted on the prototype pcb fabrication!

 :-)

[jkonstan]

Keep us posted on your progress on the FPGAARCADE board Mike.

 :-)

[jkonstan]

freqmax,

DDR VTT (1.25V) termination regulator can be linear or a buck switching regulator that was especially designed for DDR termination use.

 :-)

[jkonstan]

Ordinary buck regulators are not really designed for DDR VTT use. You may find a few that can meet the specs to be a supply for DDR VTT and for VREF on DDR. However, semiconductor companies make special regulators for VTT termination & VREF.

[jkonstan]

-Ultra-fast transient response

-VTT must sink and source current

-Low (switching noise for buck) noise on VTT

-etc ...

[jkonstan]

Check out this NSC app note for Linear VTT regulator.

http://www.national.com/an/AN/AN-1254.pdf

[jkonstan]

Mikej,

DACs tend to have poor output drive capability; thus, adding buffers (after the series cap) to the DAC outputs is a good idea. The simpliest approach is using a single ended MC33204 (VCC and GND)with a "virtual ground (VCC/2)" as a buffer or as a non-inverting amplifier so that you will not need a -VEE rail.

http://www.onsemi.com/pub_link/Collateral/MC33201-D.PDF