FPGAARCADE minimig compatible board, comments?

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Why 2x PS2 ports on opposite sides ..?
SMPS or Linear (hot-hot) regulators ..?
Configuration jumpers for video signal ..?

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Make sure one can flash the MCU (PIC) without a seperate flash hardware.

Have you provided the Vtt voltages for the DDR dram ..?
And the series termination..?, and a clock frequency of 75-133 MHz aswell ..? (or else DDR refuse to work)

@jkonstan:
Better to have P-ATA (IDE) on a external board too keep complexity and cost down for most users.

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mikej wrote:
"SMPS or Linear (hot-hot) regulators ..? "
DC-DC convertors (right hand side)

Linear DC-DC or Switched DC-DC ..?

I will post schematics when we have finished nailing the architecture for review. Its changing too much at the moment.

Many edge projects are like that. But an intermediate schematics may let others help you finding flaws directly. Or give suggestions.

DRAM has a VTT supply (linear regulator above the ram).
Parallel termination only should be ok, I'll simulate the board. Target clock speed is 166MHz (333Mbit).

Are you sure you can handle DDR SDRAM..?, it's a real pain :-)
SDR SDRAM is way simpler. And allows you to clock it from a few kHz to many MHz. And no exotic termination and signal issues.

Flexible clock generator from IDT (probably) to be added to get correct video and memory clocks.

Chip id ..? (to have a look at it)
Maybe a better solution (less jitter) than the fpga dcm.

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Which switching IC have you decided on ..?, and which inductance type?

Only provide DVI and possible VGA port. The VGA port can be (ab)used as SCART/Component/S-Video/CVBS etc..

Are you sure DDR won't work with plain I/O clock?, the Spartan-3E starter kit seems to do fine with this.
ug230.pdf

Maybe you can skip on the series termination if you can get it within 1-2 cm from the fpga? No other components should be so time critical so they can give way for the dram chip.

Is the DDR chips sensitive to SMPS power ..? (ripple)

How is SDRAM-vs-DDR1-vs-DDR2-vs-DDR3 on latency issues?, as I understand it most emulations expect single clock response from the dram memory. Ie like any first generation RAS/CAS memory module would behave. So any benefits from pipelined design with modern types of dram would be nullified. Only the video part may benefit by inserting read instructions in between. Processor access would be stalled until the requested address is returned.

An 8bit 133 MHz SDRAM should be able to handle 1024x768 18bpp 60Hz. So for this kind of emulation really heavy memory might not be needed. And even if it is, a 16bit variant would push the limit to 1600x1200 18bpp 60Hz. Way above any screen resolution I know Amiga had at least.

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Better yet.. remove RS232, PS2, JOYA, JOYB, NATGEO etc.. from the board. And and a generic I/O port. Where the functionality can be defined from the FPGA.
That enables just about any slow I/O stuff to be possible at a dirt cheap cost without cluttering the mainboard.

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Maybe PS2, but it's a slow I/O and can be outsourced to some dummy pcb with only wires. And USB hasn't been less complex since last time it was up for discussion :-)

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Board space on a board this complex comes at a hefty price. Even a central London apartment would look dirt cheap in comparision..
Thus anything that's specific and slow I/O to a certain "emulation" is preferibly put on a cheaper board that can be reused with future revisions of the main board.

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Name suggestion: "Mikes generic platform implementer v1"
By including creators name, less confusion. Generic, not limited. Platform fits both computers and arcades. And implementer avoids the culprint with emulation, simulation etc.. which is not a correct description. Clone might also be nice description.

As for killing of Dennis Minimig. It's like A2000 killing off A500.

With proper module interfaces. The SAME codebase can be used by simple replace the board specific modules. And the whole issue of diverging codebases is eliminated.
Anyway to get a chance at a 68020/AGA (A1200) implementation. A larger FPGA is a MUST.

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It's not an emulation..

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Ouch.. the impedance chores of DDR. Better stay with SDRAM
Guess we may have some reflections ..?

As for naming, it should make sense. And any words involved should be easy to say phoneticly. Or else people are most likely to call it something else very quick.

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How feasable is to make a working pcb with only one DDR memory + one FPGA in close proximity without any non-free simulation tools?, or even without?

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mikej, Any problem, especially with the pcb layout to get the LM2853 550kHz dc/dc buck converter to work alright..?, high frequency stuff tends to be nasty

Guess the composite output will be as an adapter on the DVI-I connector?

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It might be useful to have a 68020 + 68841-MMU. When your at it anyway..
A single 68030 does the same job too.

Do you have any idea on the peak di/dt of the FPGA?, it has relevance on the latancy response of the buck converter especially for the 1,2V rail.

I see you use 2,5V with linear regulator for the VTT to DDR memory. I been pondering if one can drive this with an buck converter aswell, or if the noise problems would be too great.

Guess the Minimigs get an incentive to go dynamic ram now that the fpgaarcade-replay board has 32 MB, and the Minimig has 2 MB

(your board name is FpgaArcade-Replay v0.0 ?)

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Here's an Amiga graphics roadmap:
1985 OCS  (A1000, A2000, A500)
19~~ Ranger
1990 ECS  (A3000, A500+, A600, A2000)
1992 AGA  (A1200, A4000, CD32)
1993 AAA  -  
1993 Hombre -

It should be possible to implement them all given enough hackertime

So you could select to have an A500 with AAA and SID sound.. or whatever mutation gone wrong test you want that day :-D

Ofcourse there's also the options of Picasso, or some selfdesigne graphics subsystem.

Edit: ECS/A2000

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Ie you can't use an ordinary buck converter for DDR VTT ?