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Author Topic: FastCache040+ Released!  (Read 13887 times)

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Offline SpeedGeekTopic starter

Re: FastCache040+ Released!
« Reply #14 from previous page: April 04, 2018, 02:34:55 PM »
** 8TH NEWS UPDATE **

v1.6P5 Removed code to allow PostDMA cache Flush for the case of      
       16 byte aligned transfers. Added code to skip PostDMA
       cache Flush for the case of cache disabled MEMF_24BIT
       transfers.

UPDATE:
v1.6P5 is my last attempt solve compatibility problems with
the Phase5 68060.library and Store buffer enabled. This
library is unstable and buggy WITH or WITHOUT FastCache040+
so either disable the Store buffer or expect the problems to
continue with only a MINIMAL improvement provided by this
patch!
       
v1.7 - Removed all v1.6P5 PostDMA cache flush code so most users
       (except Phase5 68060.library users) can run at full speed!

UPDATE:
Phase5 68060.library users should use v1.6P5. All others users
can (probably) use v1.4, v1.5 or v1.7 without any problems.
 

Offline SpeedGeekTopic starter

Re: FastCache040+ Released!
« Reply #15 on: April 21, 2018, 01:09:45 PM »
** 9TH NEWS UPDATE **

FastCache040+ v1.6P5 has been removed. Phase5 68060.library users should use FixMapP5 before using this patch.

FixMapP5 1.2 ©SpeedGeek 2018 (MMU Handler ©Michael Sinz 2001)
             
INTRODUCTION:
FixMapP5 is a tool to modify some of the default MMU mapping of
the Phase5 68040 and 68060 libraries. This can improve stability
and prevent crashing under the following condition:          

- Hardware or software interrupts which occur during a Chip RAM access by the 68060 (In particular when Store buffer is enabled).

Software bugs which allow illegal writes to the $F80000 Standard Kickstart ROM can cause a debugging problem in Copyback mode so this patch corrects that problem as well.

FEATURES:
- Changes Chip RAM mode to Precise (68060 only)
- Changes Standard ROM cache to Writethrough (68040 or 68060)
- Uses 68040/060 library detection code
- 100% Assembler code

REQUIREMENTS:
- Amiga with 68040 or 68060 CPU and MMU
- Phase5 68040.library or 68060.library

WARNING:
This tool was developed ONLY for use with the Phase5 libraries but
it does NOT actually verify such usage. So it can and probably
will mess up the mapping of ANY other libraries!        

CREDITS:
Thanks to Michael Sinz for his freely distributable MMU handler.

HISTORY:
v1.0 - First release
v1.1 - Added code to skip mapping $F00000 space (which included $F80000 space) for CyberstormPPC, CyberstormMK3 and BlizzardPPC
v1.2 - Replaced FindName() with FindResident() since v1.1 wasn't working at all. Also, fixed a typo on module names.
« Last Edit: April 28, 2018, 12:11:52 AM by SpeedGeek »
 

Offline SpeedGeekTopic starter

Re: FastCache040+ Released!
« Reply #16 on: May 19, 2018, 07:30:09 PM »
** 10TH NEWS UPDATE **

v1.8 Released!
- Reworked the code to eliminate a serious (but seldom noticed) data  transfer corruption bug for the case of multiple DMA drivers in the same  system. Special Thanks to Ralph Babel for his excellent knowledge on  this topic.
 

Offline SpeedGeekTopic starter

Re: FastCache040+ Released!
« Reply #17 on: May 21, 2018, 04:59:07 PM »
** 11TH NEWS UPDATE **

v1.9 Released!
- Fixed "D2 Register Not Preserved" coding bug in PreDMA.
Most DMA drivers don't seem to need it preserved but
Thanks to Cosmos for reporting it anyway. Moved PostDMA
Nest count code to user section of code. This eliminates
any calls to Supervisor when the count is more than 1.
v1.9BR Added new "Experimental" code which should allow only
DMA targeted 16MB blocks of Fast RAM to change to Write
Through mode. This "In Theory" allows the other 16MB
 blocks to remain in Copyback mode. This can only benefit
 "Big RAM" systems with 32MB+ of Fast RAM and ONLY when
 these systems run apps which use the extra Fast RAM.
 WARNING: Use at you own risk!

CACHEDMABENCH:
v1.0 - First release
v1.1 - Fixed address and size bugs in FC loop code which
could have affected the results.
 

Offline SpeedGeekTopic starter

Re: FastCache040+ Released!
« Reply #18 on: October 21, 2018, 05:33:12 PM »
** 12TH NEWS UPDATE **

FixMapP5 1.3 released

v1.3 - Swapped order of 68040/060 library test. Some OS 3.1
systems use a dummy 68040.library (which does not expunge)
and prevented the chip RAM change to precise. Thanks to
Northway for reporting this bug.
 

Offline SpeedGeekTopic starter

Re: FastCache040+ Released!
« Reply #19 on: October 23, 2018, 02:21:48 PM »
** 13TH NEWS UPDATE **

FixMapP5 1.4 released

v1.4 - Added code to determine the Chip RAM start address from the
       system memory list. Hopefully, this solves the problem with
       Kickstart versions which config the Chip RAM differently. 
 

Offline SpeedGeekTopic starter

Re: FastCache040+ Released!
« Reply #20 on: November 25, 2018, 04:52:13 PM »
** 14TH NEWS UPDATE **

FastCache040+ 2.0 released.

2.0 - Added code to enable only one DTTR when the Nest count
is one. Most systems have only one DMA driver and only need to
have 16MB of address space managed for this case.
Removed 1.9BR version which was over-rated due to most DMA
drivers operating at higher priority than typical user tasks.
« Last Edit: December 20, 2018, 07:23:02 PM by SpeedGeek »
 

Offline SpeedGeekTopic starter

Re: FastCache040+ Released!
« Reply #21 on: December 20, 2018, 07:22:12 PM »
** 15TH NEWS UPDATE **

FastCache040+ 2.1 released

v2.1 - Reworked the code to fix a problem with Snoopy 2.0 (Aminet).
Sorry, this version no longer supports 16 byte aligned cache enabled
MEMF_24BIT transfers. NOTE: The original P5 library functions have
problems with Snoopy too. I suppose FastCache040+ 2.0 should remain
available for the non-snoopers.

@Pyromania
Positive comments are always welcome!  :)
« Last Edit: December 20, 2018, 07:24:44 PM by SpeedGeek »
 

Offline SpeedGeekTopic starter

Re: FastCache040+ Released!
« Reply #22 on: December 24, 2018, 01:49:49 PM »
** 16TH NEWS UPDATE **

FastCache040+ 2.2 released

v2.2 - The Snoopy fix broke MEMF_24BIT transfers. So another
bug fix was required. Let's hope it's the last.
 

Offline SpeedGeekTopic starter

Re: FastCache040+ Released!
« Reply #23 on: December 18, 2019, 01:34:18 AM »
** 17TH NEWS UPDATE **

FastCache040+ 2.0 is no longer available and 2.2 is now the recommended version for all users. 2.2 is a little slower than 2.0 but it is also much more stable than 2.0. I was able to use 2.2 with the P5 68060.library (without FixMapP5) and there was only an occasional "Recoverable Alert" but never any hard crashing on my A3000/A3660 system.

THOR reported finding no instability problems at all with the P5 68060.library on his A2000/2060 system so there appears to be some hardware issues complicating the stability problem too. Hence, FixMapP5 is now optional and it's usage should be based the users determination of improved stability.
« Last Edit: December 18, 2019, 11:28:02 PM by SpeedGeek »
 

Offline SpeedGeekTopic starter

Re: FastCache040+ Released!
« Reply #24 on: March 07, 2020, 05:22:57 PM »
** 18TH NEWS UPDATE **

FastCache040+ 2.4 released.

2.3 - The 16 byte alignment code is back and now avoids the
change of cache mode for this specific case. Removed
Continue case from PreDMA since the expected results are
the same as the Non-Continue case. The cache disable test
code was removed to save the overhead of this very
uncommon case.

2.4 - Reworked PostDMA code to fix Nested call cache flush bugs.
We really don't want to forget about systems with multiple
DMA drivers do we?
« Last Edit: March 08, 2020, 02:55:04 AM by SpeedGeek »
 
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Offline SpeedGeekTopic starter

Re: FastCache040+ Released!
« Reply #25 on: October 26, 2022, 05:17:32 PM »
** 19TH NEWS UPDATE **

FastCache040+ 2.5 released!

v2.5 - Fixed another rare but possible bug with DMA transfers
crossing the 16MB boundary of the DTTR! So now (except for
MEMF_24BIT DMA transfers) both DTTRs are enabled to
manage the full 32MB of address space.
« Last Edit: October 26, 2022, 05:18:11 PM by SpeedGeek »
 

Offline SpeedGeekTopic starter

Re: FastCache040+ Released!
« Reply #26 on: March 01, 2024, 01:30:17 PM »
** 19TH NEWS UPDATE **

FastCache040+ 2.6 released!

v2.6 - The previous bug fix only worked for addresses in the 16MB
range. This fix should should now work with any address.