The memory interface on the NATAMI is much faster and uses DDR2(iirc). It's also going to have 32k or 64k cache.
Also, I believe their bus will be 32bits.
Hi,
When I initially designed the board I did a lot of analysis of the memory timings. DDR2 is not better than DDR1 in this application. DDR2 is basically optimised for faster clock speeds, the memory access time is about the same. For the speeds we can obtain with the FPGA (133-166MHz) then DDR1 is the better choice.
The memory bandwidth is not the problem, for example the 16 bit memory at 133Mhz will deliver over 4GBytes per second in burst sequential access. We are using the DRAM at the moment to emulate large amounts of static RAM, and we can get cycle accurate timing for the original hardware.
The softcores are not at the level of compatibility that I would like at the moment. The reason I have a 68000, 68030 and 68060 on daughter boards is to develop and test new softcores. As has been mentioned before, using FPGA internal SRAM as a cache can significantly increase performance.
People always complain about the cost, so for where we are now the memory system is about optimal cost/performance level.
The expansion board idea is a way to increase the performance above the basic card. We can develop boards with either real processors, or faster FPGAs with dedicated memory.
The most important thing for me is to get a stable board which can be mass produced which meets 90% of our current desires and has potential for expansion for the people that want that.
I imagine a future version without the expansion connectors and with several banks of memory instead.
4 connections to make on the layout, still on track for manufacture on Monday.
/Mike
in a bar in China....
