MiniMig with AGA

[yaqube]

I have implemented all the AGA features into the Minimig core using MikeJ's Replay board. You can watch it running on YouTube.

[youtube][/youtube]

As there is no 68020+ IP core available the TG68 CPU core is used. It runs at 7.09 MHz with no bus latency and according to SysInfo is 1.85 faster than a stock A1200.

The 64 MB of DDR SDRAM is configured as 2 MB Chip, 1.5 MB Slow, 8 MB Fast and 48 MB of extra memory which can be used as additional Chip memory. You can have 50 MB of Chip RAM in total.

[yaqube]

Just wondering, how can it be accessing so much memory if it's using a 68000 core? The 68000 only has a 24 bit address bus, which would limit it to 16MB?

The TG68 IP core has full 32-bit address bus so it can access up to 4 GB of memory space.

Nice, when will it be available to purchase?

Mike should finish the new PCB layout in a couple of days and then should have new boards made.

I'm surprised that those programs and games are running on a 68000.  I assumed (I know) that they would have used instructions limited to the 68020 instruction set??  Are there not that many actual differences in the two from the codes perspective?

Those games don't use any feature specific to 020+ CPUs. I guess it was easier for developers to have the same code base for different (OCS/AGA) versions of their games.

[yaqube]

I guess that chipmem size modifier works by adjusting mh_Upper and calling FreeMem() for the area to add? (that's how I would do it)

Actually I'm calling AddMemList() function with MEMF_CHIP attribute.

[yaqube]

Is there room inside the Minimig v1.x FPGA for your AGA core?  Or the C-One?

In Minimig V1.x FPGA definitely not but it should fit inside C-One Minimig extender FPGA. But be aware that the C-One doesn't support 24-bit video output, has no DDR memory neither dedicated system controller.

[yaqube]

An 060 100mhz would be a great option BUT would cost big $$$$

Don't tempt me :hammer:

[yaqube]

Can you please tell us the sysinfo speeds from the FPGAARCADE board ?
I realy want to now how fast the softcore speeds are and HDF speeds.

TG68K @ 7.09 MHz : 4.27 x A500 / 1.85 x A1200
TG68K.C @ 7.09 MHz : 5.81 x A500 / 2.52 x A1200

Hardfile read speed: 1900-2000 KB/s

[yaqube]

If it was possible to add a socket for a real 68060 I would probably buy one.

A daughterboard with 060 and some goodies like dedicated SDRAM, Fast Ethernet and USB ports is planned.

[yaqube]

Why just 7MHz ? Is it because of the non cached SDRAM access ? (7MHz for the CPU, 7 MHz for the Chipset, 70ns access time).

The memory bus of the Minimig runs at 7.09 MHz so it was the simplest solution. The CPU can access the bus every clock cycle if it's not used by the chipset DMA.

Looking at the numbers, the new TG68K.C execute almost one instruction per clock : it is at the performance level of a '040 !

The 16-bit opcodes are executed one per clock cycle. The performance could be even better if the data bus was 32-bit wide.

Tobias claims it can run at 40MHz on the fastest (and more expensive) cyclone II.

According to timing analysis results both these cores can run up to 20 MHz on Spartan-3E. I will try to run the CPU twice the speed of the memory clock. And with a prefetch buffer to improve memory throughput.

Is it with SPI or 4-bit SDIO ? Is DMA involved ?

24 MHz SPI, no DMA.

[yaqube]

Toccata emulation may help for that. Anyway I'd like to see 020 support before. And Cirrus||Virge emulation after 020 support :-)

The board is equipped with a 24-bit stereo audio DAC. Upgrading Paula to 16 bit and writing suitable AHI driver won't be a big problem. I'm also thinking about more sophisticated solution.

There is still a lot of unused memory bandwidth which can be used for implementation of an advanced flicker-fixer or graphics board (although implementation of CL/S3 chips seems to be impossible).

Both the AHI and P96 require at least 020 CPU and this is the next design object.

[yaqube]

can we hope for future version aga/060 ?

Yes, we can.

[yaqube]

Tell us what do you have holding back from us !!

I'll tell you when it's done

[yaqube]

Would be nice if yaqube could do another video! *nudge nudge*

I will make another video clip when there is something worth showing. Now I'm busy doing other things.

[yaqube]

The advantage of replicating the WinUAE hardware RTG card is that we have the source code to hand and know how its supposed to work.

The WinUAE Amiga side P96 driver is closed source. Nevertheless the Minimig on the Replay board will have a true-colour RTG board and dedicated P96 driver (yes, I will write it). It won't happen before the 020 compatible CPU core is available (guess why).

The AGA chipset will be enhanced with chunky modes very soon. The chip memory bus access is already contention free but will be improved significantly in the near future.

[yaqube]

Will the built-in chunky modes comply to any existing standard? Graffiti springs to mind.

Yes, the memory organization of chunky display buffer will be linear (as expected). The memory organization of high/true colour modes will be decided during implementation.

BTW Graffiti doesn't use standard display memory organization.

[yaqube]

Can you guy's concider to put a RTC on the expansion board if possible ?

Yes, I'm currently working on it.