Minimig v1.1 ARM Hardfile Demonstration

[whiteb]

Ummmm, my normal minimig only has 2MB on the board, I take it this one has new ram or something, or does the ARM contain RAM that configs as well ?

According to the Youtube comments, Ram was "Piggy Backed", you cannot just plop on two more chips and have them work surely ?

I thought you would at least need to separate them via Address lines ?

[whiteb]

I see from the link Darrin supplied he is using the Extra I/O plug to (I think) route signals to the new chips no doubt a couple of address lines.  That is Soldering FAR IN ADVANCE of my own.

[edit] actually, that could VERY WELL be it.

From memory, the 68882 occupied *A LOT* of the same signals that the 68xxx occupied, You just had to select the specific address lines that the chip used.  I do not know the pin outs of the chip, it looks like one pin may be bent up, and wire'd, maybe a "CS" (Chip Select) line, with the rest coexisting signals that both chips use ?

[edit2]  Yeah, if that is indeed pin 6 in the picture, that is CE (Chip, Enable input).  You just disable that pin on the FPGA, the Existing chips will NEVER receive CE, and it will ignore EVERYTHING ELSE (or how i understand it).

[whiteb]

weirdami wrote:
if that ram chip piggy backing thing works then why aren't manufacturers doing it to save on sockets and stuff?

Sockets are used for ease of putting in/Taking out.

This trick is done, to *DISABLE* the existing chip, in favor of the new chip.  Also, given the nature of the board, its *FRAGILE !!!!!*.  I have tried to desolder a damaged minimig, and lifted the pads in the process (hey, it was damaged), so you just solder over the top of the existing one, and just re-route the 'Chip Select' line.

This way it is ONE or the other, not both.  If it was to use BOTH ram, then you would need independent addressing (At least).

[whiteb]

Darrin wrote:
Looki ng at other news on this thread, what that demo really needs is AmigaSYS installed on that Hardfile.  

Is there one for A500/A600's ?  I think the lowest Amigasys for classic is A1200/4000 etc (AGA).

Unless you mean ClassicWB, they all need 68020+.

[whiteb]

darksun9210 wrote:
awesome stuff :-)

idea... how difficult would it be to have a minimig with an A500 compatible sideslot/edgeconnector?

Larger FPGA (more I/O), larger board.

[whiteb]

Darrin wrote:

Ah so this was a "safer" way to replace the existing RAM chips without having to remove them?

Precisely.  Solder the chips directly on to the old ones, and route the new CS signal over the Spare I/O.

The new chips are 10ns too, so that alone makes the Minimig compatible with that 1943 clone

[whiteb]

Illuwatar wrote:
Clever idea by yaqube with the piggy backing. But he is not disabling the original 2 MB SRAM on the board - he adds an extra 2 MB (making up these 4 MB total). The CS1-pin (nr 6) are used to choose what half of the 2 MB that will be used. All other pins are connected in parallel - that is normal and should be like that. Even on a standard 2 MB MiniMig, all pins except of CS1 are connected in parallel. The core of the FPGA has been modified to provide four chip select signals instead of just two.

Are you sure ?  The signal is a CS (Chip Select), its one OR the other.  CS means one or the other, not both.  And if the chips were to be used concurrently, they would need separate address lines. (Read, not enough I/O on the FPGA).

Whats stopping us from putting higher density with the same trick ?

[whiteb]

68000's are HIGHLY overclockable, and they dont need heat sink's

The default 68000's in the Minimig's are 16Mhz clocked by the core to 7Mhz.