MiniMig + PowerPC = OS4 Hardware for all

[HenryCase]

downix wrote:
No, that's not what he said.  He said that free clones of SPARC and MIPS CPU's exist.  You can find both on the opencores.org website.  SPARC is an open standard, Sun even released the code to their high-end UltraSPARC T1.  MIPS, however, is not, and true clones are liable for lawsuit due to patents.  Same with PowerPC.

Damn. Well, thanks for clearing this up for me downix.

Slightly OT, I was looking around the opencores.org website yesterday, came across this device:
http://www.opencores.org/projects.cgi/web/usbhostslave/overview
If the 68k core is integrated into the MiniMig FPGA, freeing up enough I/O capacity, this seems like a cheap way of adding the much requested USB functionality to the MiniMig. Of course we'd have to write our own drivers for it.

Incidentally, wouldn't there be legal repercussions if the 68k chip was emulated in FPGA form? And could we be sued by the A500 custom chip patent holders (I doubt OCS is open source)?

[downix]

HenryCase wrote:

downix wrote:
No, that's not what he said.  He said that free clones of SPARC and MIPS CPU's exist.  You can find both on the opencores.org website.  SPARC is an open standard, Sun even released the code to their high-end UltraSPARC T1.  MIPS, however, is not, and true clones are liable for lawsuit due to patents.  Same with PowerPC.

Damn. Well, thanks for clearing this up for me downix.

Slightly OT, I was looking around the opencores.org website yesterday, came across this device:
http://www.opencores.org/projects.cgi/web/usbhostslave/overview
If the 68k core is integrated into the MiniMig FPGA, freeing up enough I/O capacity, this seems like a cheap way of adding the much requested USB functionality to the MiniMig. Of course we'd have to write our own drivers for it.

Incidentally, wouldn't there be legal repercussions if the 68k chip was emulated in FPGA form? And could we be sued by the A500 custom chip patent holders (I doubt OCS is open source)?

Unless you have a beefy CPU (like a 25Mhz 68030) then USB would still bog you down.  Now, that being said, if you could expand the MiniMig's RAM, you could add an embedded controller for it, and handle it like a firewire for data transfers, and like PS/2 for mouse/keyboard, but then you'd need a bigger FPGA.  I've used that core in a few projects, never had an issue with it.

The OCS patents expired a few years back.

[mdwh2]

AndrewBell wrote:

JosephC wrote:
I did not sign any contract relinquishing my right to patch a program to run on a newer model of CPU.  I am free to patch my AmigaOS as I see fit.

Go and read the license agreement that appears during AOS install before you say that. I've never read it myself, but most commercial software imposes terms and conditions that you agree to by installing, or sometimes even opening the package.

You don't have to agree to anything by installing. It's not worth worrying about unless Amiga Inc manage to get all EULAs accepted as valid in a court of law.

[mdwh2]

AndrewBell wrote:
Even if it isn't demanded, you can run OS4 on AGA. Besides that, look at the bigger picture. Clone-A and Minimig, if available on PCI cards, offer Amiga graphics facilities to modern, fast CPUs. They still have features that are not present on modern 3D accelerated gfx cards, such as sprites, collision detection, playfields, hardware scrolling etc. Jens has even talked about extending the capabilities of the chipset.

Surely all of these things can be reproduced on modern hardware? Sprites can be done in hardware, certainly. Scrolling can be done with texture mapping, and would be at least as fast as the Amiga's hardware scrolling, surely.

[downix]

mdwh2 wrote:

AndrewBell wrote:
Even if it isn't demanded, you can run OS4 on AGA. Besides that, look at the bigger picture. Clone-A and Minimig, if available on PCI cards, offer Amiga graphics facilities to modern, fast CPUs. They still have features that are not present on modern 3D accelerated gfx cards, such as sprites, collision detection, playfields, hardware scrolling etc. Jens has even talked about extending the capabilities of the chipset.

Surely all of these things can be reproduced on modern hardware? Sprites can be done in hardware, certainly. Scrolling can be done with texture mapping, and would be at least as fast as the Amiga's hardware scrolling, surely.

if you brute force it, maybe.  But remember, it takes a multi-Ghz CPU to emulate a cycle-inaccurate version of the chipset as/is.  To make it a true clone, you'd be pushing multiple multi-core CPU's just to handle the chipset.

The Amiga's blitter alone is incredibly difficult to copy in simulation.  It's design is more akin to an ancient Crey than it is to traditional hardware, resulting in a huge overhead to make it accurate.  When you look at the cost, a pair of $1400 CPU's or a $35 FPGA... which is the cost efficient method?

[mdwh2]

downix wrote:

mdwh2 wrote:

AndrewBell wrote:
Even if it isn't demanded, you can run OS4 on AGA. Besides that, look at the bigger picture. Clone-A and Minimig, if available on PCI cards, offer Amiga graphics facilities to modern, fast CPUs. They still have features that are not present on modern 3D accelerated gfx cards, such as sprites, collision detection, playfields, hardware scrolling etc. Jens has even talked about extending the capabilities of the chipset.

Surely all of these things can be reproduced on modern hardware? Sprites can be done in hardware, certainly. Scrolling can be done with texture mapping, and would be at least as fast as the Amiga's hardware scrolling, surely.

if you brute force it, maybe.  But remember, it takes a multi-Ghz CPU to emulate a cycle-inaccurate version of the chipset as/is.  To make it a true clone, you'd be pushing multiple multi-core CPU's just to handle the chipset.

The Amiga's blitter alone is incredibly difficult to copy in simulation.  It's design is more akin to an ancient Crey than it is to traditional hardware, resulting in a huge overhead to make it accurate.  When you look at the cost, a pair of $1400 CPU's or a $35 FPGA... which is the cost efficient method?

It's difficult to reproduce the exact same behaviour (as UAE shows), so sure, if you want to run Amiga games, an FPGA may be better than emulating on standard hardware.

But I was talking about whether modern hardware have these same features. By saying "Minimig, if available on PCI cards, offer Amiga graphics facilities to modern, fast CPUs. They still have features that are not present on modern 3D accelerated gfx cards", I was reading that as suggesting this would offer something to PC users? Or did he just mean in the context of running old Amiga games?

[AeroMan]

But I was talking about whether modern hardware have these same features. By saying "Minimig, if available on PCI cards, offer Amiga graphics facilities to modern, fast CPUs. They still have features that are not present on modern 3D accelerated gfx cards", I was reading that as suggesting this would offer something to PC users? Or did he just mean in the context of running old Amiga games?

Modern graphics boards are way more powerful than AGA was. AGA had some features that are not reproduced today, like many modes on the same screen, sprites and dual playfields, but these features are nice to memory limited systems. Sprites are quite useless today, as 2d games are rare, and they can be reproduced.

I think PCs could use some Amiga like techniques, like screens. They can simulate this using modern hardware (why Aros doesn't have this ? Or am I having problems to find it :-D )

I Would like also to have genlocking stuff in modern gfx cards. That was really cool stuff !

[SamuraiCrow]

downix wrote:

jkonstan wrote:
OS4 is PowerPC based; thus, a PowerPC solution is best practical option.

OS4 is just OS 3.1 ported to PowerPC, so I understand, I'm sure folk with more know-how can be more clear on this.  But, being that, there is no practical reason for locking it onto PowerPC.  Infact, I'd almost say it would be smarter to keep the OS on m68k and use a fast JIT emulator to bring it to other CPU's, a la Amithlon.

Having seen the AmigaOS 4 SDK, I can tell you that you are 100% wrong on OS 4 being a direct port of 3.1 .  You have to use a bunch of macros just to be able to compile the old pre-OS4 source codes on it due to some extensive changes in the Exec.library functionality.  Most of Exec.library was scrapped in favor of new functionality.

As for locking it onto PowerPC, the only part of OS4 that is "locked in" is the Petunia JIT compiler.  If OS4 could be ported to LLVM or some other JIT compiler then there would be no need for any sort of "lock in".

[HenryCase]

Been having some more thoughts on how to do this Minimig+PPC solution for new OS4 h/w. I'm trying to work out the different ways Amigas were able to be upgraded with fast co-processors. Considering the Minimig is currently A500 compatible (mostly), I have focused on the A500/A2000 solutions. I have a few questions:

1. Which one of the custom chips in the A500 controlled access to the side expansion slot?
2. On the A2000, what chip was mainly responsible for control of the CPU fast slot (as far as I can tell it is likely to be either the Buster, Paula or Gary OCS chips)?
3. How did the A2000 handle having so many expansion slots at once? Did it have a chip that switched between Zorro slots for instance, or were all devices running simultaneously?
4. Of all the connectors/ports/sockets found on this list (http://www.amiga-hardware.com/connlist.cgi), which is likely to be the easiest to implement (not counting the connections the Minimig already has)?

The question that is causing most confusion for me is question 3. The A500 side expansion slot is 86pin, the A2000 CPU Fast Slot is 86pin, and I can't find a OCS chip that has enough pins to deal with either (Buster OCS is 50pin, Paula OCS is 48pin and Gary OCS is 48pin). How was it done? How do PCs do it (something to do with the Northbridge/Southbridge combo AFAIK)?

Thanks in advance.

[downix]

HenryCase wrote:
Been having some more thoughts on how to do this Minimig+PPC solution for new OS4 h/w. I'm trying to work out the different ways Amigas were able to be upgraded with fast co-processors. Considering the Minimig is currently A500 compatible (mostly), I have focused on the A500/A2000 solutions. I have a few questions:

1. Which one of the custom chips in the A500 controlled access to the side expansion slot?

CPU-driven only.  I've been working on a modified MiniMig to give it a similar expantion capability

2. On the A2000, what chip was mainly responsible for control of the CPU fast slot (as far as I can tell it is likely to be either the Buster, Paula or Gary OCS chips)?

CPU, again

3. How did the A2000 handle having so many expansion slots at once? Did it have a chip that switched between Zorro slots for instance, or were all devices running simultaneously?

they were running simul, but switched access to the memory bus.  Buster drove these

4. Of all the connectors/ports/sockets found on this list (http://www.amiga-hardware.com/connlist.cgi), which is likely to be the easiest to implement (not counting the connections the Minimig already has)?

A500 CPU-style slot

The question that is causing most confusion for me is question 3. The A500 side expansion slot is 86pin, the A2000 CPU Fast Slot is 86pin, and I can't find a OCS chip that has enough pins to deal with either (Buster OCS is 50pin, Paula OCS is 48pin and Gary OCS is 48pin). How was it done? How do PCs do it (something to do with the Northbridge/Southbridge combo AFAIK)?

Thanks in advance.

The CPU slots were just that, CPU slots.  They were directly off of the main CPU bus.

[HenryCase]

Thanks for your reply downix, helpful as always.

I'm glad to hear you're working on a modified Minimig that gives it A500-like expansion capability. It would be a great leap forward for the future of the Minimig if this can be achieved.

So the CPU drives the main CPU bus, makes sense. However, I still don't quite understand how it was done. The A500 used a 68000 processor, most of which are 64pin (there are some 68pin variants out there). How did a 64pin chip interface with a 86pin expansion slot? Seems to me that the only way would be to send the information in serial rather than parallel. If the information was sent serially, how many pins of the CPU did the expansion slot need for communication?

Thanks again.

[AJCopland]

If you can find the schematics which were in the original a500 manual you'll see that there's more than just data and address going through that connector but things like power, ground, clock (as in bus clock not the time) etc as well. Can't remember what else off the top of my head.

Not every pin of a 68k was mapped directly too the connector only the relevant parts basically.

[HenryCase]

AJCopland wrote:
If you can find the schematics which were in the original a500 manual you'll see that there's more than just data and address going through that connector but things like power, ground, clock (as in bus clock not the time) etc as well. Can't remember what else off the top of my head.

Not every pin of a 68k was mapped directly too the connector only the relevant parts basically.

Thanks for the info AJCopland.

Don't remember seeing those schematics in the manuals that came with my A500, but it has been a while since I looked through them. I take it the schematic I'm looking for is in the User's Manual rather than the Amiga Basic one? Or am I looking for something like this...
http://www.amiga-stuff.com/images/A500SystemSchematics.gif

[downix]

HenryCase wrote:
Thanks for your reply downix, helpful as always.

I'm glad to hear you're working on a modified Minimig that gives it A500-like expansion capability. It would be a great leap forward for the future of the Minimig if this can be achieved.

So the CPU drives the main CPU bus, makes sense. However, I still don't quite understand how it was done. The A500 used a 68000 processor, most of which are 64pin (there are some 68pin variants out there). How did a 64pin chip interface with a 86pin expansion slot? Seems to me that the only way would be to send the information in serial rather than parallel. If the information was sent serially, how many pins of the CPU did the expansion slot need for communication?

Thanks again.

Power, some timing signals.

I made an adaptor once, for instance, that put a thin PSU into a side expantion, getting rid of my brick.  You can power the whole board through the slot if you so desired.  But it's still pretty much just direct access to the CPU bus.

My own design, mind you, is technically the same bus, but at 3.3v rather than 5v.  That way you could add 5v should you desire using a basic adaptor, or use more modern 3.3v peripherals instead.

[AJCopland]

Yeah you could find those or alternatively I could give you this link to the a500schema.zip I found earlier :-D

Which shows you a whole buncha schematics and the one called scanp9.jpg is the one you want. If you do some googling I think you should be able to find more info about them names used etc.

Andy

[HenryCase]

@AJCopland

Went away to find the schematics, didn't realize you had posted them. Tried to download from that link, for some reason the files would open. Anyway, managed to find the Amiga 500 schematics elsewhere online:
http://machina.amigahellas.gr/stuff/A500schem.zip

In fact the site has schematics for A2000, A3000, A1060 and A590 as well:
http://machina.amigahellas.gr/amiga.html

Looking at page 9 of the A500 schematics I can see the Expansion P1A/P1B socket, which I assume is what you were referring to. Picture is here:
http://img45.imageshack.us/img45/4619/expansionzo0.jpg
Did a bit of work to analyze it. Didn't get very far, quite difficult to see the text, here's what I got:

Code: [Select]


1----------2    GND----BR----GND
3----------4    GND----BR----POW
5----------6     UN----BR----POW
7----------8     UN----------POW
9----------10    UN----------POW
11----------12   UN----------GND(CONFIG)
13----------14   GND----------_CCKQ
15----------16  CDAC----------_CCK
17----------18 _OVA----------XADY
19----------20  _INT2----------UN
21----------22   A(X)----------_INT6
23----------24   A(X)----------A(X)
25----------26    GND----------A(X)
27----------28   A(X)----------A(X)
29----------30   A(X)----------A(X)
31----------32  _FC(X)----------A(X)
33----------34  _FC(X)----------A(X)
35----------36  _FC(X)----------A(X)
37----------38      GND----------A(X)
39----------40      A(X)----------_IPL(X)
41----------42    A(X)----------_IPL(X)
43----------44    A(X)----------_IPL(X)
45----------46      A(X)----------_BEEA
47----------48    A(X)----------_VPA
49----------50    GND----------E
51----------52   _VMA----------A(X)
53----------54   _RST----------A(X)
55----------56   _HLT----------A(X)
57----------58    A(X)----------A(X)
59----------60    A(X)----------_BR
61----------62    GND----------_BGACK
63----------64    D(X)----------_BG
65----------66    D(X)----------_DTACK
67----------68    D(X)----------A_W
69----------70    D(X)----------_LDS
71----------72    D(X)----------_VDS
73----------74    GND----------_AS
75----------76    D(X)----------D(X)
77----------78    D(X)----------D(X)
79----------80    D(X)----------D(X)
81----------82    D(X)----------D(X)
83----------84    D(X)----------D(X)
85----------86    GND----------D(X)

Key:
GND - Ground
UN - Unused
BR - Bridged connection
CDAC - ?
_OVA - ?
_INT2 - Found on 8520
A(X) - Found on HN62402 (DMA?).Also found on 8520, Gary, Agnus and 68000.
_FC(X) - Found on 68000 CPU
_VMA - ?
_RST - ?
_HLT - ?
D(X) - Found on HN62402 (DMA?). Also found on 8520, Gary, Agnus and 68000.
POW - Power
GND (CONFIG) - My guess would be for self-testing h/w plugged into the expansion port
_CCKQ - Found on Agnus/Gary
_CCK - Found on Agnus/Gary
XADY - ?
_INT6 - ?
_IPL(X) - Found on Paula
_BEEA - Found on 68000 CPU
_VPA - ?
E - Found on 68000 CPU
_BR - ?
_BGACK - Found on 68000 CPU
_BG - ?
_DTACK - Found on 68000 CPU
A_W - ?
_LDS - ?
_VDS - ?
_AS - ?


Is the HN62402 the DMA controller? Are the A(X)/D(X) lines a central bus lines linking chips together? If anyone noticed spelling mistakes, please let me know.

downix:
I made an adaptor once, for instance, that put a thin PSU into a side expantion, getting rid of my brick. You can power the whole board through the slot if you so desired. But it's still pretty much just direct access to the CPU bus.

My own design, mind you, is technically the same bus, but at 3.3v rather than 5v. That way you could add 5v should you desire using a basic adaptor, or use more modern 3.3v peripherals instead.

Sounds pretty cool downix. I'm looking forward to the time I can design my own hardware. With the whole 3.3v/5v thing, I heard certain FPGAs run on 3.3v but are 5v tolerant, so that they can still run on a 5v supply. Would that be useful for the Minimig (i.e switching between 3.3v expansion cards and 5v expansion cards)?