Which was exactly *my* point. Thankyouverymuch for finally drinking the Kool-Aid.
Soap box time.
The problem is that the definition of "bitness" has changed over time. Today, it's pretty much the logical address / pointer size. Nobody really cares what the ALU and maximum integer operand size is, though in any architecture with general purpose registers (ie can be a pointer or integer) they tend to be the same width for obvious reasons.
In the early 80s, it was all about the ALU register / data bus size. 8-bit CPUs had 8 bit registers and did operations 8 bits at a time and performed 8-bit data transfers to/from memory/io.
However, every one of them that springs immediately to mind could use a pair of 8-bit register to define a 16-bit address. Most could even perform 16-bit register pair manipulation, for example incrementing or decrementing a whole 16-bit address at once. However, nobody ever considered them as anything other than strictly 8-bit.
In the 16-bit era, this paradigm was largely unchanged but architectures were starting to vary significantly. Some kept the 8-bit model of using pairs of registers to represent an address but individual registers, the ALU and data bus were still 16-bit.
Others, like our much loved 680x0 took a much longer term view. The 68000 had 32-bit wide registers for address and data. The ALU still worked on 16-bit halves at a time, transferred data 16 bits at a time and missed some 32-bit operations (32x32 multiply for example). However, it could still do the majority of 32-bit operations directly in hardware.
We called it 16-bit for want of a better description. It fit because of the data bus width/alignment but it didn't fit the internal register model nearly as well.
Under the current logical address/pointer size definition, it's definitely 32-bit. Nobody gives a rat's bumhole that it only had 24 of the 32 address bits exposed to the outside, neither did many early 32-bit processors or 64-bit ones. Physical connectivity is an implementation detail, especially when considering an architecture as a whole and not just a given chip in the family.
The 68020 is more clearly 32-bit in that it's ALU and data bus are 32-bit, but the EC version still has only 24 address bits exposed. The 32-bit era is where ALU and logical address size were really matched for the first time for almost all architectures. And that's where the "bitness" definition began to change to the present one. There were machines with 64-bit data / ALU but they didn't break the 32-bit logical address space. I guess the 4GiB limit became the new envelope to push against as processors were getting fast enough at crunching data but couldn't easily work on large enough sets of it.
Whether the 68000 is 16 or 32-bit simply depends on which decade's thinking you look at it from.
