IBM Power PC 1GHz chip only runs properly at 933MHz

[Hammer]

@ Matt_H

Not to mention better power consumption and better instruction efficiency per cycle

Did you factor in the "Pentium M"?

Note with Pentium Classic's FPU bug i.e.
1. a workaround was issued (similar to Erratum 8's remedy). This was deemed to be unacceptable in market place due to nature of legacy software’s bias.  
2. replace the product with a new product.

[Hammer]

Probably, just point them to the errata pages for x86 chips.

Note that, Intel has offered to replaced the flawed products i.e. for Pentium Classic(FPU bug) and early Pentium III 1.13Ghz(factory over-clocking).

I don’t recall AMD was guilty of early PentiumIII 1.13Ghz style factory overclocking for their Athlon chips. Their errata ussually involve with instruction bugs in certain batches e.g. Jpeg bug in certain early K7s batches*(pre-year 2000) and Opteron's REP MOVS** instruction(fixed with micro-code*** update)

*AMD has offered to replace them.
**Mainstream compliers don’t use these instruction combinations.
***Standard practise since P6 days.

[Hammer]

You can also tell them about the recent Opteron bug (don't remember what exactly though).

Note that, down clocking K8s wouldn’t fix the REP MOVS instruction set issues. This micro-coding update also reveals differences between K7 and K8 core.

AMD has issued a micro-code update (via BIOS distribution) for REP MOVS instruction set. The issuing of micro-code updates was a standard practice since P6 days. After applying microcode update; the fix is transparent enough for every day usage (unlike IBM's remedy).  

"Such a combination was likely only to occur when people were creating code in assembler, and not when using compilers" paraphrase from AMD.

[Hammer]

Not the 1GHz Itanium that had to be run at 800MHz for a similar flaw.

Note the 'Itanium 2 Processor Replacement' program (e.g. HP).

In Oz, it would be illegal to claim a product can do 1Ghz then say it can’t do 1Ghz and then offer 800Mhz workaround remedy. Breach of Trades Practise Act (TPA) Section 52 and 53.

PS; The new topic is about PPC not other processors.

[Hammer]

Or tell them about the 3.6GHz P4, thermal throttling (clockspeed reduction) kicks in when it gets to hot, so much in fact that an older 3.4GHz will run faster. It'll only run at full speed with water cooling!

PIV on the desktop works fine at 3.6Ghz; but with appropriate ventilation (as dictated by Intel’s thermal requirements). There's no need for water cooling. Refer to Alienware's Area-51 Extreme PC as an example of doing it right.  

Some vendors don’t follow Intel’s guidelines, thus the activation of the safety feature.

Note that Intel’s early PentiumIII 1.13Ghz with PIV-EE’s level of cooling wouldn’t fix the problem.

[Hammer]

Those PC users should read the doc, a workaround is possible:

Those mainstream PC users are only interested in product replacements and micro-code updates (transparent** after applying the BIOS updates).

Code substitution requires a code rewrite on all effected assembler code. How many assembler lines in a typical LinuxPPC distro (e.g. SUSE) again (rhetorical question)?

**Transparent to the existing software’s POV.

[Hammer]

Meanwhile, didn't Intel have to recall their first batch of GHz P4s after squeezing them out under similar pressure? (All proverbial ten they shipped to be able to claim they got there on time?)

IF they replace the flawed products then it’s almost a no issue. Code substituting is required IF IBM intends to transfer the (IBM's own making) bug fixing duties to the software vendors.

A product replacement/micro-coding updates negates that need for third party software vendors to patch their software.

Early Intel Pentium III @1.13Ghz flaws only effects LinuxX86 (an example) but they run reasonably fine with Windows.  Intel could have told those Linux users to do a code substitute trick, but the LinuxX86 markets demands product replacement and they got it.

[Hammer]

@KennyR  

CPU vendors have to minimise the cause of heat generation by employing technologies such as Low-K Black Diamond i.e. heat is generated due to electron leakage.

Intel is already at +6Ghz on some section of the PIV chip.

[Hammer]

To Intel who had had a previous perfect record (apart from the P5 bug) this was unacceptable,

In regards to "previous perfect record", note the micro-code updates and secondary purpose of micro-coding engine in P6 product lines. I still have those micro-code [d]update[/d] patches with my PC-Chips747 CD.

Secondly, Intel has direct competitive pressures coming from AMD i.e. it looks bad on them when they have issues with Linux. During that time Intel was fighting a rear guard action (mindshare). Except from AMD, not one company has the power to affect Intel’s bread and butter(it's core biz) e.g. the iAMD64 extensions on IA-32.  
 
These pressures involve reliability, legacy running (without user intervention code substitutions) and clock speed (the design of Pentium IV** is a response for AMD's K7 clockspeed romp).

My statement on "LinuxX86 markets demands product replacement and they got it." is due to implied market pressure.

**AMD changes the rules of engagement with XP and K8.

[Hammer]

But do you really believe they'll scale down CPUs for less heat when they dump silicon for diamond?

Refer to the principle of heat generation in fusing wires to each end of a battery i.e. the wire gets hotter. The electron leakage is basically runs on the similar principle.
Low-K Black Diamond promotes lower consumption, hence less heat generation.

Low-K Black Diamond dielectric is already in use on
1. AMD's K8 @90 nm.
2. ATI's DX9 VPU e.g. ATI Radeon 9600.  

Note why ATI’s VPU is relatively cooler than their NV counterpart i.e. both has similar transistor count and clockspeeds. This is where AMD and IBM differ in 90nm migration.

Black Diamond Low k is product of Applied Materials Inc.

Reference
http://news.moneycentral.msn.com/ticker/sigdev.asp?Symbol=TSM

"Applied Materials' Black Diamond low-k dielectric to provide faster performance and lower power consumption."

Both IBM (PPC970 90 nm) and Intel are on SS (Strain Silicon) camp.

[Hammer]

Which is a pity...because I'm beginning to look for a new x86 machine to replace my ancient Cyrix P200, and so far none I've spotted have an acceptable performance/heat ratio.

Atm, I don't have specific access to Cyrix P200's Amp and voltages values for comment.

I recall, Cyrix M II @300MHz's max power is at ~24W , 3.0Volts, 8Amp. 16Watt grade Barton(uPGA)(laptop) or Pentium M(laptop) or Apple iBook can this easily.

[edit]
Cyrix
6x86 PR200+ (150MHz),20.77W, 25.20W(Max power)
6x86L PR200+ (150MHz), 14.28W, 17.69W(Max power)
6x86MX PR200 (166MHz),11.50W, 19.10W(Max power)

All easy targets for X86 mobile/PPC32 processor (not including desktop replacement processors).

[Hammer]

@http://www.chipworks.com/chipnews/2002_i02/interconnect_2.htm
Refer to
http://www.appliedmaterials.com/products/copper_interconnect_films.html
Applied Materials Inc's Low-K information/marketing material.

[Hammer]

The VIA CPUs aren't much more powerful than my Cyrix (even at 800MHz!)

Note that both AMD's Geode GX/120x (from Cyrix GX core) and VIA’s C3(from Cyrix M3 core) is based from Cyrix technology.

**Geode NX(PGA Socket A) is based from K7 core (relative of 16W grade Barton uPGA Socket A).

[Hammer]

Scary numbers from the slot CPU era:
http://grassomusic.de/english/amdk7.htm
(In editing for width, I note that Xoops takes poorly to links containing '?' options.)

Refer to
http://myplc.com/sony/docs/amd_processor_reference.html
for volt and amps values.

PS; The table doesn’t include the latest Sempr0n (Socket A), Barton 400FSB (Socket A), Geode NX (Socket A), Thornton (Socket A), 130nm CG stepping K8 and 90nm D0 stepping K8s,

[Hammer]

@minator  

Refer to
http://news.com.com/2009-1040-251312.html?legacy=cnet
http://www.national.com/news/item/0,1735,329,00.html

VIA's early Cyrix III (Joshua, Jedi, Gobi) was based on native x86 Cayenne core. In was later dropped in 2000 in favor of Centaur's WinChip/C5/Samuel. After employing Samuel core, VIA was still using Cyrix III label but this was shorten to just 'C3'. The C3 that I’m referring to is the x86 Cayenne core.

National's Cyrix group(before the buyout by VIA in 1999)has Cyrix MIII (M3, Jalapeno core, Mojave),
It's was an out-of-order, decoupled design (translate x86 to uops) and it has 11 stages.

The usage of "and VIA’s C3(from Cyrix M3 core) is based from Cyrix" statement is for Kenny’s performance/power ratio.

KennyR’s statement about Cyrix PR200’s performance/power ratios can be easly reach by today’s VIA C3 MPU. Using Cyrix PR200 as an example of performance/power ratio reference would be considered to be very poor in the light of AMD's Geode NX/16Watt&35Watt grades K7-AXPs, Intel's Pentium M and VIA's C3(Nehemiah).