Enter the DRAGON

[PulsatingQuasar]

MCF5475 Features
V4e ColdFire core with MMU, dual precision FPU and EMAC - delivering up to 410 (Dhrystone 2.1) MIPS at 266 MHz
32 KB I-Cache, 32 KB D-Cache
32 KB on-chip system SRAM
Four 32-bit timers, two 32-bit slice timers, one watchdog timer
Hardware-acceleration encryption (DES, 3DES, RC4, AES, MD5, SHA-1, RNG)
32-bit 133 MHz DDR/SDR-SDRAM Controller
1.5V core, 2.5V DDR, 3.3V I/O voltages
Connectivity Functionality:

Two 10/100 Fast Ethernet Controllers (FECs)
USB 2.0 high speed device with integrated PHY
32-bit v2.2 PCI interface; 33/66 MHz; five external masters
DSPI - SPI with DMA capability
I2C interface
16-channel DMA controller


I wonder which 68K instructions are missing and how often they are used? Nice specs though.

EDIT - from the manual.

The ColdFire instruction set is a simplified version of the M68000 instruction set. The removed instructions include BCD, bit field, logical rotate, decrement and branch, and integer multiply with a 64-bit result.

How often are these used?

The manual does note many differences with the 68000 but also gives additions and tips on how to use the missing CPU/FPU instructions.

[PulsatingQuasar]

I'm beginning to speculate here but this 32 KB on-chip system SRAM could be used for software to add the missing 68K instructions. I don't know if it's possible but it would in theory be a nice place to do that.

I saw several places in the manual where they talked about the differences between the 68K and the Coldfire and how to do things alternatively when porting source to the coldfire.

Maybe the developer kit from Freescale had allready source to implement all the missing functions of the 68K as a service to industrial companies looking for a quick fix to replace their old 68K stuff. I mean, the 68K might still be in use in the industry.

For an anounced date of january this hardware must actually be already finished. It's real release data would then be dependent on the delivery in quantaties of that coldfire.

Keeping an eye out for this hardware.

[PulsatingQuasar]

Hmmm....read somewhat more through the documentation.

10.2.3.6 Supervisor/User Stack Pointers
To isolate supervisor and user modes, CF4e implements two A7 register stack pointers, one
for supervisor mode and one for user mode. Two former M680x0 privileged instructions to
load and store the user stack pointer are restored in the instruction set architecture.

and

The FPU programming model is like that in the
MC68060 microprocessor. {but is 64-bit instead of 80-bit. I don't know what that means when you want to run MC68K code}

[PulsatingQuasar]

@DaNi

Well, with the BlizzardPPC you loose a lot of time with context switching. So depending on how much CPU time is lost with adding the missing bits to the Coldfire I won't be suprised if it runs the 68K version of Quake 2 faster.