« Reply #46 on: May 07, 2012, 09:56:39 PM »
According to
Wikipedia:
The processor has two unidirectional 32-bit double data rate (DDR) buses (one for reads, the other for writes) to the system controller chip (northbridge) running at one quarter of the processor core speed. The buses also carry addresses and control signals in addition to data so only a percentage of the peak bandwidth can be realized (6.4 GB/s at 450 MHz). As the buses are unidirectional, each direction can realize only half the aggregate bandwidth, or 3.2 GB/s.
So not exactly optimal (
why oh why is there still address/data multiplexing in this day and age!?) but a damn sight better than the G4.

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