The only reason this sloppy E clock timing works at all is because the 8520 CIA is not a Motorola 6800 peripheral chip. If it was, this 14 MHz accelerator design would fail. Commodore designed these custom chips for the Amiga and using the E clock to drive them somewhat simplified the Amiga's I/O hardware design.
That's the impression that I got reading the 68000 datasheet and noting that the Amiga has no actual M6800 peripherals.
But just because you can sometimes get away with sloppy timing does not means it's often good idea to do so.
Definitely.
The fundamental timing problem is still not corrected because @ 28 MHz the CPU's E clock cycle will end in one 7 MHz clock. A more reliable way to handle this problem is to disable the CPU E clock cycle by disconnecting VPA and connecting a pull-up resistor. You then add logic to generate VMA when the E clock is low and keep it latched when the E clock is high.
That's a point. Currently /VMA is unconnected on the PCB (and per the schematic), I guess there's an internal pullup...? What's the consequence of the short E pulse?
Here are some example boolean logic equations:
/VMA = /E * /VPA # /VMA * E
I did not find the pound sign (#) in the list of standard boolean operators. What did you mean?
Next you need to generate ETERM to terminate the cycle:
/ETERM.D = ETERM * E * /AS * /VMA
/EDTACK.D = EDTACK * /AS * /ETERM
/DTACK.D = DTACK * /AS * /EDTACK
/DTACK.T = DTACK * /AS * /EDTACK
NOTE: ETERM and EDTACK are registered on the rising edge of the 7 MHz clock (but you can experiment with the falling edge). DTACK is registered on the 14 MHz clock. Also, DTACK is a Tri-State signal.
I'm not familiar with the .D and .T notation. What did you mean? ETERM and EDTACK symbols are connected to what?
As far as creating the proper 60/40 duty cycle, that's probably not as important as having the E clock at the proper frequency and having the rising edge synchronized with the 7 MHz clock.
I found a dedicated divider part that will generate the proper frequency E pulse in under 1ns. That will definitely get it working, at least on par with the unmodified 14MHz accelerator. I like the fact that it keeps with the minimalist spirit of the original project in OP. But latching with the rising edge of the 7MHz clock is definitely something that I can do. I also found a decade counter that would let me generate it from the 7MHz reference.
The main reason to keep the correct duty cycle is performance concerns.
Yeah, I had a hunch about that, are you able to quantify what is affected by the pulse width?
BTW, some 68020+ systems can be modified for improved performance. Here is the link:
https://forum.amiga.org/index.php?topic=74945.msg850556
Nice project, useful toward "Amiga-like computer from scratch" projects that don't use any original Amiga components (which will be my final goal, eventually). Thanks for providing the code. I wouldn't mind learning that type of PLD syntax/notation. I'm more fluent with VHDL and Verilog.
So the unmodified 14MHz accelerator has a problem I noted a while back. I have an ide68k+mem68k sandwich, and it does not work at all with the 14MHz accelerator, I get flashing colors when I power on the machine. At 28MHz I get a black screen with this peripheral. Unfortunately I don't have them separately so I don't know which of them has the problem, I got this peripheral with one of my A1000. It does work properly with the stock 7MHz 68000. Do you have any idea what could be the issue? I might give it a closer look next week to see which signals are connected so I could eliminate some factors. I will be building two kinds of IDE interface, so need to put together BOMs for that.
I need to gather parts lists from multiple projects, then I'll be able to continue with this. I like to build large carts to save on shipping. I really like the lists feature on DigiKey as it lets me keep BOMs for projects.
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