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AuthorTopic: FastCache040+ Released!  (Read 2749 times)

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Offline SpeedGeek

Re: FastCache040+ Released!
« Reply #15 on: October 17, 2017, 12:34:52 AM »
Quote from: Thomas Richter;831804
No wonder, there's nothing in your system that calls CachePre/PostDMA(), even though it should. Thus, a rather pointless exercise on your side.

There are reasons for these functions, and what this patch essentially does is that it disables or bypasses one of the functionalities the functions should have.

Their API is certainly not very wisely designed, though that is not a reason to break them...

The A3000 scsi.device uses these functions, and just in case you didn't know Commodore was testing the 040 CPU prototype card (which eventually was replaced by the A3640) on the A3000 long before the A4000 was released!

« Last Edit: October 17, 2017, 02:15:15 AM by SpeedGeek »

Offline matt3k

Re: FastCache040+ Released!
« Reply #16 on: October 17, 2017, 01:14:13 AM »
Lol I didn't notice that.  Funny.  Yes using mycpu060.  Love auto spell correct.

Offline SpeedGeek

Re: FastCache040+ Released!
« Reply #17 on: October 23, 2017, 04:39:06 PM »
Ok, here are images of the new improved benchmark tool. Sadly, only 1 user has provided compatibility results so far? :rolleyes:

Offline SpeedGeek

Re: FastCache040+ Released!
« Reply #18 on: October 28, 2017, 04:42:41 PM »

The new benchmark tool has now been released! The lamers who failed to  provide compatibility feedback owe a BIG THANKS to the users who did. A  very special Thanks to thebajaguy for providing feedback on multiple systems! :)

BTW, these benchmark results were easily predictable. It's a No-Brainer!

Offline SpeedGeek

Re: FastCache040+ Released!
« Reply #19 on: March 30, 2018, 02:45:03 PM »

v1.5 - Found an occasional Recoverable Alert bug which could
possibly result in a crash but only on 060 systems!
The simple fix was to move "CINVA NC" in PostDMA to the
end of the code.
- Removed the "+" character from the executable name due
to a unknown "Feature" of the Amiga Shell causing script
execution and version command problems.

EDIT: [CPU060 NOWRITEBUFFER] with the Phase5 46.7 68060.library seems to  be a more reliable solution than the v1.5 update. Some more testing is  required.
« Last Edit: March 31, 2018, 01:57:44 AM by SpeedGeek »

Offline SpeedGeek

Re: FastCache040+ Released!
« Reply #20 on: April 01, 2018, 05:50:24 PM »

v1.6 - Added code to PostDMA to Flush the cache conditionally
       (if the Store buffer and cache are enabled). Added NOPs
       to sync the pipelines before RTE (CINVA is now obsolete)

68040 users can use v1.4 or v1.5 if they like since they will
be a little faster than v1.6 but 68060 users should use v1.6!
68060 users will now have a performance trade off to consider
in deciding whether to enable the store buffer.

Offline SpeedGeek

Re: FastCache040+ Released!
« Reply #21 on: April 04, 2018, 02:34:55 PM »

v1.6P5 Removed code to allow PostDMA cache Flush for the case of      
       16 byte aligned transfers. Added code to skip PostDMA
       cache Flush for the case of cache disabled MEMF_24BIT

v1.6P5 is my last attempt solve compatibility problems with
the Phase5 68060.library and Store buffer enabled. This
library is unstable and buggy WITH or WITHOUT FastCache040+
so either disable the Store buffer or expect the problems to
continue with only a MINIMAL improvement provided by this
v1.7 - Removed all v1.6P5 PostDMA cache flush code so most users
       (except Phase5 68060.library users) can run at full speed!

Phase5 68060.library users should use v1.6P5. All others users
can (probably) use v1.4, v1.5 or v1.7 without any problems.

Offline SpeedGeek

Re: FastCache040+ Released!
« Reply #22 on: April 21, 2018, 01:09:45 PM »

FastCache040+ v1.6P5 has been removed. Phase5 68060.library users should use FixMapP5 before using this patch.

FixMapP5 1.2 ©SpeedGeek 2018 (MMU Handler ©Michael Sinz 2001)
FixMapP5 is a tool to modify some of the default MMU mapping of
the Phase5 68040 and 68060 libraries. This can improve stability
and prevent crashing under the following condition:          

- Hardware or software interrupts which occur during a Chip RAM access by the 68060 (In particular when Store buffer is enabled).

Software bugs which allow illegal writes to the $F80000 Standard Kickstart ROM can cause a debugging problem in Copyback mode so this patch corrects that problem as well.

- Changes Chip RAM mode to Precise (68060 only)
- Changes Standard ROM cache to Writethrough (68040 or 68060)
- Uses 68040/060 library detection code
- 100% Assembler code

- Amiga with 68040 or 68060 CPU and MMU
- Phase5 68040.library or 68060.library

This tool was developed ONLY for use with the Phase5 libraries but
it does NOT actually verify such usage. So it can and probably
will mess up the mapping of ANY other libraries!        

Thanks to Michael Sinz for his freely distributable MMU handler.

v1.0 - First release
v1.1 - Added code to skip mapping $F00000 space (which included $F80000 space) for CyberstormPPC, CyberstormMK3 and BlizzardPPC
v1.2 - Replaced FindName() with FindResident() since v1.1 wasn't working at all. Also, fixed a typo on module names.
« Last Edit: April 28, 2018, 12:11:52 AM by SpeedGeek »

Offline SpeedGeek

Re: FastCache040+ Released!
« Reply #23 on: May 19, 2018, 07:30:09 PM »

v1.8 Released!
- Reworked the code to eliminate a serious (but seldom noticed) data  transfer corruption bug for the case of multiple DMA drivers in the same  system. Special Thanks to Ralph Babel for his excellent knowledge on  this topic.

Offline SpeedGeek

Re: FastCache040+ Released!
« Reply #24 on: May 21, 2018, 04:59:07 PM »

v1.9 Released!
- Fixed "D2 Register Not Preserved" coding bug in PreDMA.
Most DMA drivers don't seem to need it preserved but
Thanks to Cosmos for reporting it anyway. Moved PostDMA
Nest count code to user section of code. This eliminates
any calls to Supervisor when the count is more than 1.
v1.9BR Added new "Experimental" code which should allow only
DMA targeted 16MB blocks of Fast RAM to change to Write
Through mode. This "In Theory" allows the other 16MB
 blocks to remain in Copyback mode. This can only benefit
 "Big RAM" systems with 32MB+ of Fast RAM and ONLY when
 these systems run apps which use the extra Fast RAM.
 WARNING: Use at you own risk!

v1.0 - First release
v1.1 - Fixed address and size bugs in FC loop code which
could have affected the results.

Offline SpeedGeek

Re: FastCache040+ Released!
« Reply #25 on: October 21, 2018, 05:33:12 PM »

FixMapP5 1.3 released

v1.3 - Swapped order of 68040/060 library test. Some OS 3.1
systems use a dummy 68040.library (which does not expunge)
and prevented the chip RAM change to precise. Thanks to
Northway for reporting this bug.

Offline SpeedGeek

Re: FastCache040+ Released!
« Reply #26 on: October 23, 2018, 02:21:48 PM »

FixMapP5 1.4 released

v1.4 - Added code to determine the Chip RAM start address from the
       system memory list. Hopefully, this solves the problem with
       Kickstart versions which config the Chip RAM differently. 

Offline SpeedGeek

Re: FastCache040+ Released!
« Reply #27 on: November 25, 2018, 04:52:13 PM »

FastCache040+ 2.0 released.

2.0 - Added code to enable only one DTTR when the Nest count
is one. Most systems have only one DMA driver and only need to
have 16MB of address space managed for this case.
Removed 1.9BR version which was over-rated due to most DMA
drivers operating at higher priority than typical user tasks.
« Last Edit: December 20, 2018, 07:23:02 PM by SpeedGeek »

Offline Pyromania

Re: FastCache040+ Released!
« Reply #28 on: November 27, 2018, 03:18:06 AM »

Thanx for the release and the hard work.

Offline SpeedGeek

Re: FastCache040+ Released!
« Reply #29 on: December 20, 2018, 07:22:12 PM »

FastCache040+ 2.1 released

v2.1 - Reworked the code to fix a problem with Snoopy 2.0 (Aminet).
Sorry, this version no longer supports 16 byte aligned cache enabled
MEMF_24BIT transfers. NOTE: The original P5 library functions have
problems with Snoopy too. I suppose FastCache040+ 2.0 should remain
available for the non-snoopers.

Positive comments are always welcome!  :)
« Last Edit: December 20, 2018, 07:24:44 PM by SpeedGeek »