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AuthorTopic: C64 FPGA Idea  (Read 5949 times)

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Offline trekiej

C64 FPGA Idea
« on: May 08, 2011, 09:43:11 AM »
I was wondering if some one thought about widening the bus for the 6510 processor.
Eight bit opcode and an eight bit or 16 bit operand for a fpga c64 sound interesting.
Amiga 2000 Forever :)
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Offline vidarh

Re: C64 FPGA Idea
« Reply #1 on: May 08, 2011, 12:15:11 PM »
Quote from: trekiej;636500
I was wondering if some one thought about widening the bus for the 6510 processor.
Eight bit opcode and an eight bit or 16 bit operand for a fpga c64 sound interesting.


There is already a *real* 16 bit replacement for the 6510, the WDC 65816, designed by Bill Mensch, one of the original 6510 designers. It was available from 1984, and has been used in the Apple IIgs for example, and is still manufactured as well as possible to license as a core for ASICs. There's also a drop-inc 6502 compatible version, the 65802, but that's more limited for obvious reasons (no wider external bus)

Since there's been accelerators for the C64 using it too, I'm sure someone will do an FPGA version eventually if there isn't one already.
 

Offline trekiej

Re: C64 FPGA Idea
« Reply #2 on: May 08, 2011, 12:23:32 PM »
I have heard of the 65C816 and have one.
Maybe some one could do a core for the MCC 216.
Amiga 2000 Forever :)
Welcome to the Planar System.
 

Offline gaula92

Re: C64 FPGA Idea
« Reply #3 on: May 08, 2011, 01:45:05 PM »
The 65C816 was Super Nintendo's main CPU, too :D
 

Offline Digiman

Re: C64 FPGA Idea
« Reply #4 on: May 08, 2011, 03:27:16 PM »
Quote from: gaula92;636525
The 65C816 was Super Nintendo's main CPU, too :D


And it was ripped a new one by Sega's 16bit console with 68000 launched 2 years earlier ;)
 

Offline omnicron10

Re: C64 FPGA Idea
« Reply #5 on: May 08, 2011, 06:42:03 PM »
The Chameleon is a C64 cart that offers an accelerated 6510 CPU for the c64 and more ram, drive emulation along with a VGA output.  It is all in beta at the moment but progressing well.  

A minimig core with 020 and 8 megs of fast ram was just released as well.

The Chameleon also supports a standalone mode that does not need to be connected to a C64 to operate.

http://www.syntiac.com/chameleon.html
A500/030 40mhz with A530, Indivision ECS, , KS 3.1, 2 Megs Chip, 8 Megs fast.
A600 Vampire II
SAM440EP 667, Amiga OS 4.1u1
Dual G4 1.2 Mac MorphOS
Chameleon
CD32
SX64
128D
128
C64
64C
 

Offline trekiej

Re: C64 FPGA Idea
« Reply #6 on: May 08, 2011, 08:12:23 PM »
I would like a chameleon too.
I am wondering if a wider buss is possible in the design.
I hear that the c64 has a 256 byte memory page.
It is suppose to be faster if one keeps code inside that page instead of trying to move
Address H and Address L all the time.
Amiga 2000 Forever :)
Welcome to the Planar System.
 

Offline vidarh

Re: C64 FPGA Idea
« Reply #7 on: May 08, 2011, 08:40:50 PM »
Quote from: trekiej;636566
I would like a chameleon too.
I am wondering if a wider buss is possible in the design.


Given that the FPGA is big enough to handle the Minimig core, I'm sure it'd be possible. It's back to whether or not someone spends the time updating the cores...

Quote

I hear that the c64 has a 256 byte memory page.
It is suppose to be faster if one keeps code inside that page instead of trying to move
Address H and Address L all the time.


Well, there are a few different things: If you want to do indexed accesses, it's faster to do that in the 256 byte zero page. Also, if you cross a 256 byte boundary I believe you incur a 1 cycle cost, so you'd want to be a bit careful about the location of tight inner loops etc. (and in demo effects it'd bite you very easily for any effects that need cycle exact timing, like DYSP). That's the ones I seem to remember off the top of my head.
 

Offline trekiej

Re: C64 FPGA Idea
« Reply #8 on: May 08, 2011, 10:56:47 PM »
My idea come from the layout of the pdp-1. It has an 18 bit instruction where it has a 12 bit operand.
If it could move a 16 bit operand in the same time as an instruction fetch, I do not doubt it could speed things up.
Amiga 2000 Forever :)
Welcome to the Planar System.
 

Offline alexh

Re: C64 FPGA Idea
« Reply #9 on: May 08, 2011, 11:05:25 PM »
Why would you want to? Surely the idea is to run as much C64 code as accurately as possible?

Widening the CPU instruction bus & data bus is pointless. All you do is introduce huge binary incompatibilities.

What you can do is :

Up the CPU clock rate.
Lower the instruction timings (fewer clock cycles per instruction).
Lower the RAM R/W timings (fewer clock cycles per read/write).

But each of these just introduces more incompatibilities.

You'd could have these features but perhaps make it a turbo mode which could be switched on specially for software which supported it? But then that means writing new software.
 

Offline HenryCase

Re: C64 FPGA Idea
« Reply #10 on: May 08, 2011, 11:13:29 PM »
Is the SuperCPU still produced?
http://www.cmdweb.de/scpu.htm
http://www.youtube.com/watch?v=_rcJ7BRbXX4

Perhaps you could get one of those to start building a software library that could use the extra power that a FPGA solution could provide?
"OS5 is so fast that only Chuck Norris can use it." AeroMan
 

Offline trekiej

Re: C64 FPGA Idea
« Reply #11 on: May 08, 2011, 11:32:31 PM »
SuperCPU, I do not believe they are still being made.

I guess it depends on if the Instruction Decode can be re-written to transparently handle it.
*******************
What you can do is :

Up the CPU clock rate.
Lower the instruction timings (fewer clock cycles per instruction).
Lower the RAM R/W timings (fewer clock cycles per read/write).
********************
These are fine by me too.
« Last Edit: May 08, 2011, 11:48:40 PM by trekiej »
Amiga 2000 Forever :)
Welcome to the Planar System.
 

Offline vidarh

Re: C64 FPGA Idea
« Reply #12 on: May 09, 2011, 10:35:48 AM »
Quote from: alexh;636616
Why would you want to? Surely the idea is to run as much C64 code as accurately as possible?

Widening the CPU instruction bus & data bus is pointless. All you do is introduce huge binary incompatibilities.


The 65816 managed it just fine, by starting in 6510 compatible mode and making you run a two instruction sequence to turn on the extra capabilities. For things like GEOS and GEOS apps and other non-timing dependent applications it should work fine. But of course most games etc. are likely to fail miserably.

I'm not sure the available C64 apps are really interesting enough to make it worthwhile other than for the hack factor, though.
 

Offline omnicron10

Re: C64 FPGA Idea
« Reply #13 on: May 09, 2011, 09:46:31 PM »
Nice thing is the Chameleon offers a nice speed bump to the C64 with out the complexity of the Super CPU and is available now.  The turbo mode can be activated with a button or in software and supports most illegal op-code unlike the 65816 in 6510 mode.

Floppy EMU, REU, VGA and other options make it real nice!  Some items are still in beta but I can tell you, it is shaping up nicely!
A500/030 40mhz with A530, Indivision ECS, , KS 3.1, 2 Megs Chip, 8 Megs fast.
A600 Vampire II
SAM440EP 667, Amiga OS 4.1u1
Dual G4 1.2 Mac MorphOS
Chameleon
CD32
SX64
128D
128
C64
64C
 

Offline gaula92

Re: C64 FPGA Idea
« Reply #14 on: May 09, 2011, 10:16:30 PM »
Quote from: omnicron10;636789
Nice thing is the Chameleon offers a nice speed bump to the C64 with out the complexity of the Super CPU and is available now.  The turbo mode can be activated with a button or in software and supports most illegal op-code unlike the 65816 in 6510 mode.

Floppy EMU, REU, VGA and other options make it real nice!  Some items are still in beta but I can tell you, it is shaping up nicely!



How does it compare with an MCC-216? Does Mayhem In Monsterland work in the Chameleon? Does Tim Follin's GHouls'n Ghosts title music sound totally right in the Chamaleon?