Is it emulation in hardware? I'm confused =)
A common question I see (not sure what it means) when it regards to FPGA is "is it cycle-exact?"
I do not consider FPGA implementations to be "emulation".
When you load the FPGA bitstream file, you are opening or closing routing connections, you are selecting inputs to multiplexors, you are telling each LUT which logic circuit it is to be (for this input value give that output value). When configuration is done, the FPGA is nto "processing" anything, it is not running software to do any of what the bitstream said. When configuration is done, the FPGA now "is" the defined circuit. All those passgates and multiplexors are now really just wires to the defined circuit. The LUTs are logic circuits. The flipflops are flipflops. There is no "emulation" which is "running" There only is a logic circuit which "is".
And the only thing that is happening is whatever your circuit is defined to do. Flipflops are flopflopping. Logic circuits are giving outputs appropriate to their inputs. Routes are wires. That's it. And there's no software or anything else operating above, below, or beside that.
If you have defined a 680x0 processor, then the 68000 processor is running 68000 software or waiting to do so. If you have defined a Zorro to PCI bus bridge, then it is converting bus cycles. If you have defined a SCSI controller, then it is controlling SCSI peripherals according to commands it receives from the host bus. If you've defined a DDR memory controller, then it is controlling DDR memory according to the host bus. That's it. If you have defined it to be an Amiga 500 with 68000 and PCI and DDR2, then it is running 68000 software, talking to PCI cards, and talking to DDR2 memory chips. Wires will clear flipflops the same way that wires clear flip-flops in custom ASIC chips. Clock signals tell flipflops to take in new values from their inputs the same way as they do in Custom ASIC chips. And gates give 1 when all inputs are 1 and otherwise 0 the same way that AND gates do in Custom ASIC chips. OR gates give a 1 output when any input is 1 value otherwise 0, same as in an ASIC. Wires conduct signals the same way as wires do in Custom ASIC chips. A 32bit CPU register is made up of 32 FPGA silicon flipflops, same as in an ASIC. Multiplexors to select datapaths in an ALU are made up of FPGA silicon multiplexors. This is hardware being routed to wire up silicon, same as logic gates are wired up in an ASIC.
It's just that the FPGA lets you change your wiring around, while an ASIC is fixed. FPGA provides a flipflop on silicon in every section. Maybe two. But it lets you skip over them if you don't want them. An FPGA can have this particular NOR gate here, or reroute and put it over there, etc. by changing which passgates are closed and which way multiplexors go. An ASIC wire is fixed by the production masks.
That's it.
In an ASIC, to connect the output of an OR gate to an inverter, you draw a wire. All silicon. In an FPGA, there are things to be OR gates and inverters on the silicon, and there's a lot of wires all over the place, which can potentially connect just about anything to anything, or disconnect anything from anything. The bitstream is read into static memory elements which control the connect or disconnect at each point, and are used to connect the various bits of silicon-level wire between your OR gate and your inverter. All hardware, all silicon.
That's it. And maybe the best way I've said it so far in this last bit.