FPGAARCADE minimig compatible board, comments?

[TheDaddy]

@all

Thanks for the explanation. :-D

[freqmax]

Make sure one can flash the MCU (PIC) without a seperate flash hardware.

Have you provided the Vtt voltages for the DDR dram ..?
And the series termination..?, and a clock frequency of 75-133 MHz aswell ..? (or else DDR refuse to work)

@jkonstan:
Better to have P-ATA (IDE) on a external board too keep complexity and cost down for most users.

[mikej]

right, in order:
"Why 2x PS2 ports on opposite sides ..?"
top connectors not fitted by default. Now it is slightly larger mini-itx size the PS2 connector will move down. Holes for box headers for the joysticks will also be added so they can be cabled off.

"SMPS or Linear (hot-hot) regulators ..? "
DC-DC convertors (right hand side)

"Configuration jumpers for video signal ..?"
yes, not placed.

I will post schematics when we have finished nailing the architecture for review. Its changing too much at the moment.

Dennis, currently a PIC18LF2520. The header on the left is for a pickit2 programmer along with a 5v supply jumper for ICP.

DRAM has a VTT supply (linear regulator above the ram).
Parallel termination only should be ok, I'll simulate the board. Target clock speed is 166MHz (333Mbit).

Flexible clock generator from IDT (probably) to be added to get correct video and memory clocks.

/Mike

[TheDaddy]

Hi Dennis,

Do you know if anyone is working on a better minimig.bin file?

I mean more compatible as at the moment these are the results:

http://www.loriano.pwp.blueyonder.co.uk/what_works.htm

Thanks :-D

[freqmax]

mikej wrote:
"SMPS or Linear (hot-hot) regulators ..? "
DC-DC convertors (right hand side)

Linear DC-DC or Switched DC-DC ..?

I will post schematics when we have finished nailing the architecture for review. Its changing too much at the moment.

Many edge projects are like that. But an intermediate schematics may let others help you finding flaws directly. Or give suggestions.

DRAM has a VTT supply (linear regulator above the ram).
Parallel termination only should be ok, I'll simulate the board. Target clock speed is 166MHz (333Mbit).

Are you sure you can handle DDR SDRAM..?, it's a real pain :-)
SDR SDRAM is way simpler. And allows you to clock it from a few kHz to many MHz. And no exotic termination and signal issues.

Flexible clock generator from IDT (probably) to be added to get correct video and memory clocks.

Chip id ..? (to have a look at it)
Maybe a better solution (less jitter) than the fpga dcm.

[wizard66]

jkonstan wrote:
Mike,

 Also, add an IDE connector via Spartan3e/level shifters (CBT16245).

 :-)

+1 ;-)

[mikej]

"Linear DC-DC or Switched DC-DC ..?"
Can you get a linear DC-DC??
I'm using switching buck converters.

I will post the schematics before layout is completed, all the reviewing I can get the better


The clocking is one of the remaining design problems. I'm looking at 2 chips, one to generate 20MHz for the PIC and a base clock for the FPGA as well as 166 for the memory controller. The other I'm looking at is an IDT307 or similar which has a PLL and can be used to generate all the odd video frequencies we may need. The DCM clk_fx output is quite noisy and can't be used for the memory interface.

Can I handle DDR? I hope so - I do this for a living but it will be tricky on a board this cheap using such a slow device. But, we could do with the bandwidth if we want high res high colour displays. I am thinking of adding a second dram chip, they are seriously cheap. SDRAM is in many cases better but it's getting harder to get hold of. I am using DDR over DDR2 as the latency is less.

I will try and fit in an IDE connector on the daughter board.

So, everybody happy with using the VGA/DVI/SCART connector on the main card and only having Composite out on the daughter card ??

/Mike

[amigadave]

TheDaddy wrote:
Hi Dennis,

Do you know if anyone is working on a better minimig.bin file?

I mean more compatible as at the moment these are the results:

http://www.loriano.pwp.blueyonder.co.uk/what_works.htm

Thanks :-D

Thanks for the list and the testing.  The rest of us surely appreciate the list of results.

[downix]

Hey Mike, you're following me now!

[jkonstan]

Mike,

The new TI spread spectrum Clock Synthesizers are nice parts as well.
 
http://focus.ti.com/docs/prod/folders/print/cdce937.html

I have seen a Spartan3 FPGA used for DDR controller where DDR clock generation was done via FPGA DLL, and it worked fairly well.

Are you going to use Hyeprlynx or another Signal Integrity tool to simulate your pcb layout ?

When you post the schematics, I will look them over.

 :-)

[freqmax]

Which switching IC have you decided on ..?, and which inductance type?

Only provide DVI and possible VGA port. The VGA port can be (ab)used as SCART/Component/S-Video/CVBS etc..

Are you sure DDR won't work with plain I/O clock?, the Spartan-3E starter kit seems to do fine with this.
ug230.pdf

Maybe you can skip on the series termination if you can get it within 1-2 cm from the fpga? No other components should be so time critical so they can give way for the dram chip.

Is the DDR chips sensitive to SMPS power ..? (ripple)

How is SDRAM-vs-DDR1-vs-DDR2-vs-DDR3 on latency issues?, as I understand it most emulations expect single clock response from the dram memory. Ie like any first generation RAS/CAS memory module would behave. So any benefits from pipelined design with modern types of dram would be nullified. Only the video part may benefit by inserting read instructions in between. Processor access would be stalled until the requested address is returned.

An 8bit 133 MHz SDRAM should be able to handle 1024x768 18bpp 60Hz. So for this kind of emulation really heavy memory might not be needed. And even if it is, a 16bit variant would push the limit to 1600x1200 18bpp 60Hz. Way above any screen resolution I know Amiga had at least.

[jensl]

Can you make 15 pol gameports, maybe for a NeoGeo port.
With a 15 pol you have more spare pins for future use.

Here a link with connectors ->
http://www.hardwarebook.info/Neo-Geo_Joystick

15 PIN D-SUB FEMALE at the console.

15 PIN D-SUB MALE at the joystick cable.

Pin    Name    Dir    Description
1    GND    ---    Ground
2    n/c    -    Not connected
3    SELECT    <--    Select Button
4    BUTTOND    <--    "D" Button
5    BUTTONB    <--    "B" Button
6    RIGHT    <--    Right
7    DOWN    <--    Down
8    n/c    -    Not connected
9    BUTTOND    <--    "D" Button, again?
10    n/c    -    Not connected
11    START    <--    Start Button
12    BUTTONC    <--    "C" Button
13    BUTTONA    <--    "A" Button
14    LEFT    <--    Left
15    UP    <--    Up

Notes:

[freqmax]

Better yet.. remove RS232, PS2, JOYA, JOYB, NATGEO etc.. from the board. And and a generic I/O port. Where the functionality can be defined from the FPGA.
That enables just about any slow I/O stuff to be possible at a dirt cheap cost without cluttering the mainboard.

[bloodline]

freqmax wrote:
Better yet.. remove RS232, PS2, JOYA, JOYB, NATGEO etc.. from the board. And and a generic I/O port. Where the functionality can be defined from the FPGA.
That enables just about any slow I/O stuff to be possible at a dirt cheap cost without cluttering the mainboard.

While I agree... but PS/2 and USB are a must really...

[freqmax]

Maybe PS2, but it's a slow I/O and can be outsourced to some dummy pcb with only wires. And USB hasn't been less complex since last time it was up for discussion :-)

[bloodline]

freqmax wrote:
Maybe PS2, but it's a slow I/O and can be outsourced to some dummy pcb with only wires.

It a must since a PS/2 keyboard is the easiest way to get Keyboard control! And who doesn't have (or can't get) a PS/2 mouse?

 And USB hasn't been less complex since last time it was up for discussion :-)

Ok, ok! But it would be nice :-)