To connect 4 IDE devices, you DO need the additional hardware to add support for another IDE channel. No playing with cables alone is going to allow you to connect more than two devices. The internal IDE controllers can only handle one IDE channel without hardware to add logic for a second IDE channel, thus only two devices on stock IDE controller period.
The Aminet link you provided is for just this sort of hardware. It's not for any cable shenanigans.
Actually the additional hardware is mostly for buffering, which allows it to go quicker somehow (if someone who understands how that works could explain then I'd appreciate it)
But getting 4 drives instead of 2 is very simple. ATA works very much like ISA, it's like a standard cpu bus. Each hard drive has 16 addresses allocated to it, but it's really only the first 8 that are really used.
Helpfully there is a separate pin that tells the drive whether the computer is accessing the first block of 8 or the second. If you feed each of those to the first block input of both drives, you can talk to 4 drives instead of 2. Essentially when you access the second block of registers of drive 0, you're actually accessing the first block of registers of drive 2.
From the standard:
http://www.t13.org/documents/UploadedDocuments/project/d0791r4c-ATA-1.pdfIt's these
| HOST CHIP SELECT 0 37 | ----- CS1FX- -------->| 37 |
| HOST CHIP SELECT 1 38 | ----- CS3FX- -------->| 38 |
The second block of registers is actually quite sparse, by not being able to access the second block you lose three things
1. being able to soft reset the drive
2. being able to disable the irq generation
3. being able to read the "alternate status", which just returns the normal status without clearing any pending irq.
I'm not sure if the original scsi.device even relies on these in the first place & you can probably gate the irq further up (in gayle or intena). Not sure whether you can control the reset line of the ata bus using gayle (I have a vague recollection that cutting that was necessary for some drives anyway).
That is what the hacked cable in the aminet package does, it should work fine with the atapifix software. It would be great if scsi.device could be extended to support it, it would probably be very trivial. You'd want to come up with a detection for it, I think you could probably do it quite easily by trying to access a register in the second block that doesn't exist but is read/write in the first block.
Looking at "7.2 I/O register descriptions"
sector count would be a good one for detection.
CS3FX- (Control block registers)
| 0 | x | X | Data bus high imped | Not used |
CS1FX- (Command block registers)
| 0 | 1 | 0 | Sector count | Sector count |
(the two CS registers are active low)
I think the amiga linux distributions support it, so it's probably worth reading how they do it (aros 68k may also support it, I haven't looked at that code in years though)