Amiga.org
Operating System Specific Discussions => Other Operating Systems => Topic started by: trekiej on March 12, 2013, 03:13:20 PM
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Are there any FPGA computers that feature a C128?
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Not that I've seen yet. Hopefully someone, some day might make a C128 core for the Chameleon64.
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Not that I've seen yet. Hopefully someone, some day might make a C128 core for the Chameleon64.
... or for FPGAReplay ... ;)
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Not that I've seen yet. Hopefully someone, some day might make a C128 core for the Chameleon64.
The dual video output makes it kinda hard. I'd prefer to see a C65 core for the Chameleon.
(not that I have one, they aren't compatible with the C128 so I got a 1541U2 instead).
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The MIST board would be perfect for this. At least you can build that one yourself. It's based around the Cyclone III and is pretty new. Supports USB rather than PS/2 ports.
I'm currently in the process of building one to run the minimig core on.
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... or for FPGAReplay ... ;)
I have a set of CBM "special character" stickers waiting to be applied to my keyboard should that happen. :D
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The dual video output makes it kinda hard. I'd prefer to see a C65 core for the Chameleon.
(not that I have one, they aren't compatible with the C128 so I got a 1541U2 instead).
Yeah, we're more likely to find a "Super 64" core more useful, with extra screen modes, expanded BASIC, more RAM, etc.
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The MIST board would be perfect for this. At least you can build that one yourself. It's based around the Cyclone III and is pretty new. Supports USB rather than PS/2 ports.
I'm currently in the process of building one to run the minimig core on.
That should be interesting. Keep us updated.
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The MIST board would be perfect for this. At least you can build that one yourself. It's based around the Cyclone III and is pretty new. Supports USB rather than PS/2 ports.
I'm currently in the process of building one to run the minimig core on.
Replay supports USB as well now.
Not so many people wish to build their own, having built a few I don't either....
/MikeJ
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Yeah, we're more likely to find a "Super 64" core more useful, with extra screen modes, expanded BASIC, more RAM, etc.
Like the SuperVIC and MonsterSID? http://c64upgra.de/c-one/ Kamelito
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Replay supports USB as well now.
Not so many people wish to build their own, having built a few I don't either....
/MikeJ
Nothing wrong with the FPGA Arcade, its a well designed feature packed board worth the asking price, if anything it will drive forward support for new minimig cores and more. I just enjoy building the boards so unless a kit is ever offered it won't be for me.
At the same time the board Till has designed in the form of the MIST is excellent and all the more amazing for the fact he designed and built the first board in just a few months :).
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Nothing wrong with the FPGA Arcade, its a well designed feature packed board worth the asking price, if anything it will drive forward support for new minimig cores and more. I just enjoy building the boards so unless a kit is ever offered it won't be for me. .
I'm happy to send you a kit of parts if you fancy building one, I find the SMD machine a bit easier though ;)
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I'm happy to send you a kit of parts if you fancy building one, I find the SMD machine a bit easier though ;)
I'll take a fully assembled board with USB :)
I could just imagine how pissed I'd be when I spend several hundred hours assembling it and it failed to work.
It would be worse than the time I typed in a several page of HEX code from RUN magazine and on completion it tuned out to be an April fools joke...
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It would be worse than the time I typed in a several page of HEX code from RUN magazine and on completion it tuned out to be an April fools joke...
That's just WRONG! Funny, but WRONG! :D
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Like the SuperVIC and MonsterSID? http://c64upgra.de/c-one/ Kamelito
Yes. Shame my C-One is dead at the moment. :(
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That's just WRONG! Funny, but WRONG! :D
My sister who spent several hours reading me HEX codes as I typed them in did not think it was very funny either....
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That should be interesting. Keep us updated.
Will do, just waiting for the minor parts now. All the major components have arrived from digikey. With this and the GBA1000 builds its going to be a fun few months.
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Like the SuperVIC and MonsterSID? http://c64upgra.de/c-one/ Kamelito
I had a C-one and none of those features ever happened.
They did finally get a c64 core working decently with the FPGA64 project and then with the FGPA upgrade PCB, there was a beta of the Chameleon 64 core.
Cool hardware but a few design issues and no complete software left a lot to be desired.
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I was ironic, I heard that Jerry lost her job at Valve, she has time now to finish the C1. Kamelito
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It seems that none of the FPGA projects worked out well for her. The C-one with IC and the Mammoth Toys deal I guess were both bust financially for her.
I would have loved to have seen a Super VIC/SID as listed in those design concept documents! I doubt the stock C-one would have had the ability to do it as well.
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@kamelito
Wow, what qualifies you to speak for Jerry and her time? I would presume that she has bills to pay and likes to eat, just as we all do. She's more than likely out looking for another job to pay her bills and buy food rather than spending it on FPGA projects that DON'T bring ANY income to her.
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@kamelito
Wow, what qualifies you to speak for Jerry and her time? I would presume that she has bills to pay and likes to eat, just as we all do. She's more than likely out looking for another job to pay her bills and buy food rather than spending it on FPGA projects that DON'T bring ANY income to her.
You can find out what she's up to:
https://twitter.com/jeriellsworth
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@kamelito
Wow, what qualifies you to speak for Jerry and her time? I would presume that she has bills to pay and likes to eat, just as we all do. She's more than likely out looking for another job to pay her bills and buy food rather than spending it on FPGA projects that DON'T bring ANY income to her.
I am unsure as to your harsh tone in this response. I agreed, I would imagine that she is looking for a good job rather than making FPGA projects. My original post stated that. I don't think anyone meant any disrespect towards Jeri.
As I posted, the C-one and the DTV projects did not work out well for her.
The DTV, although successful, Mammoth worked out the deal in such a way that she got nearly nothing from the contract.
The C-one was not a financial success for anyone.
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A C65 core sounds great and I bet a C128 is do able.
I hear that a Chameleon has an accelerator that seems to rival a Super CPU in some way.
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But the Chameleon 64 lacks SID filters and doesn't sound very well at all in standalone mode... I've asked several times in the beta testing list but they don't seem interested in implementing them. I'm thinking about selling the Chameleon 64.
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How about the MCC-216 does it have the filters?
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How about the MCC-216 does it have the filters?
I think it had some kind of filter (whatever that moron Frenchshark stole from open source solutions available), but it didn't sound true to a C64 either.
I don't have MCC-216 anymore. I'm glad I got rid of that bug-ridden POS.
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Sound like I need to get a real machine or stick with emulation.
I wish I had a FPGA Computer that has all the bells and whistles.
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@kamelito
Wow, what qualifies you to speak for Jerry and her time? I would presume that she has bills to pay and likes to eat, just as we all do. She's more than likely out looking for another job to pay her bills and buy food rather than spending it on FPGA projects that DON'T bring ANY income to her.
No disrepect here, I very much like what she's doing, I meant if she wants to... The C1 was a dream machine to me and I was disappointed so see how it end. I own 2 C64DTV, the Chameleon is interesting but it seems that it will never be out of beta. I hope that the Clone-A will come true even if I don't really know what it'll be. I just know that its for everyone not geek only. Kamelito
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Work is being done to model the SID analog filters in the digital domain.
The Replay board has a high-quality 24bit/192K DAC so it is as transparent as possible.
I don't know how close we will get, but it should be a very good approximation.
I have talked to a number of people working on this over the last few years.
/MikeJ
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The state of software emulation of the SID is already amazing! I hope the efforts made in software emulation since I first started using VICE are related to what you are speaking of, mikej.
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The state of software emulation of the SID is already amazing! I hope the efforts made in software emulation since I first started using VICE are related to what you are speaking of, mikej.
To some extent, in that the hardware analysis has already helped the software emulation.
With detailed die scans of the chip, the filters and other analogue components are understood at transistor level now. While we cannot emulate this behaviour directly in the FPGA, it is possible to model with DSP in the same way - possible better - than the software does.
/MikeJ
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Oh, which SID software emulation do you think is most accurate?
ReSid?
https://bel.fi/alankila/c64-sw/index-cpp.html
/MikeJ
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Oh, which SID software emulation do you think is most accurate?
ReSid?
https://bel.fi/alankila/c64-sw/index-cpp.html
/MikeJ
Yeah, the best I've heard is Alankila's floating point ReSID fork. Besides the lack of noise and screen buzzing, I don't think I would be able to tell it from a C64 better than I could tell a C64 from another.
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I like the C128 but an upgraded C64 in an FPGA is more attractive to me.
Something like Jiffy Dos and Simons Basic added to it and vga output.
Has anyone here ran c64 or Amiga 500 emulation on a Raspberri Pi?
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I like the C128 but an upgraded C64 in an FPGA is more attractive to me.
Something like Jiffy Dos and Simons Basic added to it and vga output.
Well the Turbo Chameleon 64 http://www.syntiac.com/chameleon.html is what you say.
It still havessome rough edges but getting better all the time. Biggest issue with an FGPA project like this is finishing it. Although the c64 is well understood, implementing a complete 100% c64 could be a never ending project.
So far it is very advanced and mature. A high level of software works and most complex items work. As noted in this thread, the SID filters are not complete but they are on a long list of items to complete.
The good news is you can use it with a real C64 and use the SID output on that for the time being.
It is the best FPGA c64 project so far. I have tried all available FPGA c64 projects and the Chameleon is the best so far.
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I have a hacked C64 DTV with a 1541 ultimate that works very well. I use the software version of jiffydos called SJLOAD for the DTV to improve transfer times on the IEC bus. I have not run into 1 game that I play that hasn't worked on the modified DTV with the ultimate. And Darrin I have used a set of those stickers on my mitsumi keyboard I picked up for the DTV, they work well.
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I am glad to hear you have such good luck with your DTV! There are also some very cool DTV only demos. The DTV has a mode with more colours than a standard c64 as well!
Here is a link to a few programs for the DTV enhanced display. http://dtvhacking.cbm8bit.com/common/photos/index.html
Which DTV do you have?
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I have a hacked C64 DTV with a 1541 ultimate that works very well. I use the software version of jiffydos called SJLOAD for the DTV to improve transfer times on the IEC bus. I have not run into 1 game that I play that hasn't worked on the modified DTV with the ultimate. And Darrin I have used a set of those stickers on my mitsumi keyboard I picked up for the DTV, they work well.
I have also a hacked dtv and i'm wondering what these stickers are. Would be cool to have the dtv keyboard with some c= appearance.
Are these stickers available to buy still?
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@ The Crow:
Just search eBay for "commodore keyboard stickers":
http://www.ebay.com/sch/i.html?_trksid=p2050601.m570.l1313&_nkw=commodore+keyboard+stickers&_sacat=0&_from=R40
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I guess the Chameleon will be the one on my list for a future buy.
What is the FPGA Arcade going for these days?
I still can not buy one. :)
Also in issue 101 of Amiga Future is a case for the Mini-mig.
Who can tell me about it?
Also has SteveJ. released his Raspberri Pi case?
Later.
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I think it had some kind of filter (whatever that moron Frenchshark stole from open source solutions available), but it didn't sound true to a C64 either.
I don't have MCC-216 anymore. I'm glad I got rid of that bug-ridden POS.
Do you know what the moron has to tell you, ******* ?
The filter is called a "state variable filter" and was done by myself.
Try to learn HDL before criticizing the others.
Bastard.
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Do you know what the moron has to tell you, ******* ?
The filter is called a "state variable filter" and was done by myself.
Try to learn HDL before criticizing the others.
Bastard.
Maybe I don't know HDL, but I don't steal other people's work either, as YOU do. You can take your faulty hardware and you "state variable filter" and stick them though you back hole.
No one in his right mind is ever buying an MCC-216 anymore once they know how bad built the thing is and how ILLEGAL (appart from incomplete and incompatible) your Amiga core is. Not to mention the C64 core, also stolen and still having all kind of bugs.
Or the AppleII core, wich can't even load a disk image.
I hope the open source developers who you scammed with your ridiculous product will protect their work from working on your hardware so you can't steal anymore.
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Maybe I don't know HDL, but I don't steal other people's work either, as YOU do. You can take your faulty hardware and you "state variable filter" and stick them though you back hole.
No one in his right mind is ever buying an MCC-216 anymore once they know how bad built the thing is and how ILLEGAL (appart from incomplete and incompatible) your Amiga core is. Not to mention the C64 core, also stolen and still having all kind of bugs.
Or the AppleII core, wich can't even load a disk image.
I hope the open source developers who you scammed with your ridiculous product will protect their work from working on your hardware so you can't steal anymore.
You are just ridiculous with your unfounded allegations based on some stuffs you have read on forums and you are constantly repeating over and over.
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Publish the sources so everyone can see that is your work.
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@kamelito
I'm with you 100%. It's so rare that anyone recreates our old 8-bit loves that it's hard not to get pushy or impatient about it......sorry if I sounded harsh.
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@Gaula92 and FrenchShark
Amiga.org is such a lively and colorful place! There's more drama here than on a b-grade soap opera! I hate to admit it, but sometimes I surf this board just for the drama. Thanks for keeping it interesting!
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Publish the sources so everyone can see that is your work.
`include "arg_defs.vh"
module Agnus /* verilator tracing_off */
(
// Main reset & clock
input rst, // Global reset
input ram_rdy, // SDRAM ready
input clk, // Master clock (28/56/85 MHz)
// Generated clocks
output cck, // CCK clock
output cdac_r, // CDAC_n rising edge
output cdac_f, // CDAC_n falling edge
output c7m_r, // CPU 7 MHz clock rise
output c7m_f, // CPU 7 MHz clock fall
output ena_28m, // 28 MHz clock enable
output [2:0] cyc_28m, // 28 MHz cycle number
output [11:0] cyc_ram, // RAM sequencer cycles
// Configuration
input cfg_ecs, // OCS(0) or ECS(1) chipset
input cfg_a1k, // Normal mode(0), A1000 mode(1)
input [3:0] cfg_chip, // Chip RAM size (512 KB - 8 MB)
// Interrupt
output int3_n, // Level 3 interrupt (Blitter)
// Video beam position
output [7:0] hpos, // Horizontal position
output lol, // Long line (228 cycles)
output eol, // End of line
output [8:0] vpos, // Vertical position
output lof, // Long field (263 or 313 lines)
output eof, // End of field
output pal_ntsc_n, // PAL (1), NTSC (0)
// DMA / Chip RAM control
input dmal, // DMA request from Paula
output [8:1] rga_out, // Register address bus out
input [15:0] db_in, // Data bus input
output reg [15:0] db_out, // Data bus output
output [15:0] db_out_er, // Data bus output (early read)
output [22:1] addr_out, // Chip RAM address output
output bus_we, // Chip RAM write enable
output bus_req, // Chip RAM requested by Agnus
output dma_req, // DMA requested by Agnus
output ram_ref, // Chip RAM refresh request
// Cache control
output [4:0] chan_out, // DMA channel number
output cache_hit, // DMA cache hit
output flush_line, // Flush current write cache line
// Address decoding
input [8:1] rga_in, // Register address bus in
input rregs_dmac, // DMACONR decoding
input rregs_vp, // VPOSR decoding
input rregs_vhp, // VHPOSR decoding
input wregs_copc, // COPCON decoding
input [10:0] wregs_blt, // BLTxxxx decoding
input wregs_cjp1, // COPJMP1 decoding
input wregs_cjp2, // COPJMP2 decoding
input wregs_cins, // COPINS decoding
input wregs_diwb, // DIWSTRT decoding
input wregs_diwe, // DIWSTOP decoding
input wregs_ddfb, // DDFSTRT decoding
input wregs_ddfe, // DDFSTOP decoding
input wregs_dmac, // DMACON decoding
input wregs_bplc, // BPLCON0 decoding
input wregs_beam, // BEAMCON decoding
input wregs_diwh, // DIWHIGH decoding
input wregs_fmod // FMODE decoding
);
// Clock input frequency : 28/57/85 MHz
parameter MAIN_FREQ = 85;
// Internal wires
wire w_cdac_r;
wire w_cdac_f;
wire w_cck;
wire w_ena_28m;
wire [2:0] w_cyc_28m;
wire [7:0] w_hpos;
wire w_lol;
wire w_eol;
wire [8:0] w_vpos;
wire w_lof;
wire w_eof;
wire w_vblend;
wire [1:0] w_strb;
wire w_refr;
wire w_ptr_rd_ena;
wire [9:2] w_ptr_rd_rga;
wire [22:0] w_ptr_rd_val;
wire w_mod_rd_ena;
wire [8:1] w_mod_rd_rga;
wire [22:1] w_mod_rd_val;
wire w_pos_rd_ena;
wire [8:2] w_pos_rd_rga;
wire [8:0] w_spr_vstart;
wire [8:0] w_spr_vstop;
wire w_ptr_wr_ena;
wire [8:2] w_ptr_wr_rga;
wire w_cpu_wr_ena;
wire w_cop_dma;
wire [22:1] w_cop_pc;
wire w_cop_hit;
wire w_one_dot;
wire w_ptr_inc;
wire w_ptr_dec;
wire w_mod_add;
wire w_mod_sub;
wire [4:0] w_chan_out;
wire w_bst_ena;
wire w_blt_last;
wire w_bus_we;
//////////////////////////////////
// Register memory write access //
//////////////////////////////////
reg r_regs_wr_p2;
reg [8:1] r_rga_p2;
reg [15:0] r_db_in;
always@(posedge rst or posedge clk) begin
if (rst) begin
r_regs_wr_p2 <= 1'b0;
r_rga_p2 <= 8'hFF;
r_db_in <= 16'h0000;
end else if (cdac_r) begin
// Global write to register memory
if ((rga_in[8:1] != 8'hFF) && (rga_in[8:5] != 4'h0))
r_regs_wr_p2 <= 1'b1;
else
r_regs_wr_p2 <= 1'b0;
r_rga_p2 <= rga_in;
if (cck) r_db_in <= db_in;
end
end
assign w_cpu_wr_ena = r_regs_wr_p2 & cck;
/////////////////////
// Registers read //
////////////////////
wire w_BBUSY;
wire w_BZERO;
wire [15:0] w_DMACONR;
wire [15:0] w_VPOSR;
wire [15:0] w_VHPOSR;
always@(posedge rst or posedge clk) begin
if (rst) begin
db_out <= 16'h0000;
// Rising edge of CDAC_n with CCK = 0
end else if (cdac_r & ~cck) begin
db_out <= ( w_DMACONR & {16{rregs_dmac}} )
| ( w_VPOSR & {16{rregs_vp }} )
| ( w_VHPOSR & {16{rregs_vhp }} );
end
end
// DMACONR bits
assign w_DMACONR[15:12] = { 1'b0, w_BBUSY, w_BZERO, 1'b0 };
assign w_DMACONR[11:8] = { 1'b0, r_BLTPRI, r_DMAEN, r_BPLEN };
assign w_DMACONR[7:4] = { r_COPEN, r_BLTEN, r_SPREN, 1'b0 };
assign w_DMACONR[3:0] = 4'b0000; // Bits 4-0 are in Paula
// VPOSR bits
`ifdef AGNUS_PAL
assign w_VPOSR[15:8] = { w_lof, 7'h20 }; // 8372 rev 4 PAL
`else
assign w_VPOSR[15:8] = { w_lof, 7'h30 }; // 8372 rev 4 NTSC
`endif
assign w_VPOSR[7:0] = { w_lol, 6'b000000, w_vpos[8] };
// VHPOSR bits
assign w_VHPOSR[15:8] = w_vpos[7:0];
assign w_VHPOSR[7:0] = w_hpos[7:0];
//////////////////////////
// DMA control register //
//////////////////////////
reg r_BLTPRI;
reg r_DMAEN;
reg r_BPLEN;
reg r_COPEN;
reg r_BLTEN;
reg r_SPREN;
wire w_BPLEN;
wire w_COPEN;
wire w_BLTEN;
wire w_SPREN;
always@(posedge rst or posedge clk) begin
if (rst) begin
r_BLTPRI <= 1'b0;
r_DMAEN <= 1'b0;
r_BPLEN <= 1'b0;
r_COPEN <= 1'b0;
r_BLTEN <= 1'b0;
r_SPREN <= 1'b0;
end
// Rising edge of CDAC_n with CCK = 1
else if ((cdac_r) && (cck)) begin
if (wregs_dmac) begin
if (db_in[15]) begin
// Set
r_BLTPRI <= r_BLTPRI | db_in[10];
r_DMAEN <= r_DMAEN | db_in[9];
r_BPLEN <= r_BPLEN | db_in[8];
r_COPEN <= r_COPEN | db_in[7];
r_BLTEN <= r_BLTEN | db_in[6];
r_SPREN <= r_SPREN | db_in[5];
end
else begin
// Clear
r_BLTPRI <= r_BLTPRI & ~db_in[10];
r_DMAEN <= r_DMAEN & ~db_in[9];
r_BPLEN <= r_BPLEN & ~db_in[8];
r_COPEN <= r_COPEN & ~db_in[7];
r_BLTEN <= r_BLTEN & ~db_in[6];
r_SPREN <= r_SPREN & ~db_in[5];
end
end
end
end
assign w_BPLEN = r_BPLEN & r_DMAEN;
assign w_COPEN = r_COPEN & r_DMAEN;
assign w_BLTEN = r_BLTEN & r_DMAEN;
assign w_SPREN = r_SPREN & r_DMAEN;
/////////////////////////
// Address computation //
/////////////////////////
wire w_next_line;
wire [22:1] w_ptr_inc_val;
wire [22:1] w_ptr_val;
reg [22:0] r_ptr_wr_val;
reg [22:1] r_addr_out;
reg r_cache_hit;
reg r_flush_line;
reg r_bus_we;
assign w_next_line = w_one_dot // One dot mode
| w_mod_add // Add modulo
| w_mod_sub // Subtract modulo
| ( (&w_ptr_rd_val[3:1]) & w_ptr_inc) // Increment 7->0
| (~(|w_ptr_rd_val[3:1]) & w_ptr_dec); // Decrement 0->7
assign w_ptr_inc_val = { {21{w_ptr_dec}}, w_ptr_inc | w_ptr_dec };
assign w_ptr_val = w_ptr_rd_val[22:1] + w_ptr_inc_val;
always@(posedge rst or posedge clk) begin
if (rst) begin
r_ptr_wr_val <= 23'd0;
r_addr_out <= 22'd0;
r_cache_hit <= 1'b0;
r_flush_line <= 1'b0;
r_bus_we <= 1'b0;
end else if (cdac_r & ~cck) begin
// Muxer between DMA pointer and Copper's PC
if (w_cop_dma) begin
// Copper DMA
r_addr_out <= w_cop_pc & { cfg_chip, 18'b111_11111111_1111111 };
r_cache_hit <= w_cop_hit & r_BSTMODE[4];
end else begin
// Other DMA
r_addr_out <= w_ptr_rd_val[22:1] & { cfg_chip, 18'b111_11111111_1111111 };
r_cache_hit <= (w_ptr_rd_val[0] | w_bus_we) & w_bst_ena;
end
// Write cache flush
r_flush_line <= (w_blt_last | w_next_line | ~w_bst_ena) & w_bus_we;
// Write enable (Disk or Blitter)
r_bus_we <= w_bus_we;
// Compute next address (with cache hit flag)
if (w_mod_add) begin
// Add modulo
r_ptr_wr_val[22:1] <= w_ptr_val + w_mod_rd_val;
end else if (w_mod_sub) begin
// Subtract modulo
r_ptr_wr_val[22:1] <= w_ptr_val - w_mod_rd_val;
end else begin
// Increment/decrement address
r_ptr_wr_val[22:1] <= w_ptr_val;
end
r_ptr_wr_val[0] <= ~w_next_line;
end
end
assign addr_out = r_addr_out;
assign chan_out = w_chan_out;
assign cache_hit = r_cache_hit;
assign flush_line = r_flush_line;
assign bus_we = r_bus_we;
....
does it look like Minimig to you ?
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And for the fun the scheduler ROM of the VIC-II :
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY video_vicII_rom_sched IS
PORT(
-- ROM clock
clock : IN STD_LOGIC;
-- ROM address
addr : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- ROM read enable
rdena : IN STD_LOGIC;
-- ROM data
dout : OUT STD_LOGIC_VECTOR(29 DOWNTO 0)
);
END video_vicII_rom_sched;
ARCHITECTURE rtl of video_vicII_rom_sched IS
TYPE ROM_type IS ARRAY(0 TO 255) OF STD_LOGIC_VECTOR(29 DOWNTO 0);
CONSTANT sched_rom : ROM_type :=
(
------------------------------------
-- NTSC chip (65 cycles per line) --
------------------------------------
-- cycle: access: hcount:
"001110010111111110000000000100", -- 13/14 VIC 000 \
"001110010111111110000000000000", -- 13/14 CPU 004 | Refresh
"001110000111111110000000000100", -- 15 VIC 008 /
"001110000111111110000000000001", -- 15 CPU 00C \
"001110000111111110000000000010", -- 16 VIC 010 |
"001110000111111110000000000001", -- 16 CPU 014 |
"001110000111111110000000000010", -- 17 VIC 018 |
"001110000111111110000000000001", -- 17 CPU 01C |
"001110000111111110000000000010", -- 18 VIC 020 |
"001110000111111110000000000001", -- 18 CPU 024 |
"001110000111111110000000000010", -- 19 VIC 028 |
"001110000111111110000000000001", -- 19 CPU 02C |
"001110000111111110000000000010", -- 20 VIC 030 |
"001110000111111110000000000001", -- 20 CPU 034 |
"001110000111111110000000000010", -- 21 VIC 038 |
"001110000111111110000000000001", -- 21 CPU 03C |
"001110000111111110000000000010", -- 22 VIC 040 |
"001110000111111110000000000001", -- 22 CPU 044 |
"001110000111111110000000000010", -- 23 VIC 048 |
"001110000111111110000000000001", -- 23 CPU 04C |
"001110000111111110000000000010", -- 24 VIC 050 |
"001110000111111110000000000001", -- 24 CPU 054 |
"001110000111111110000000000010", -- 25 VIC 058 |
"001110000111111110000000000001", -- 25 CPU 05C |
"001110000111111110000000000010", -- 26 VIC 060 |
"001110000111111110000000000001", -- 26 CPU 064 |
"001110000111111110000000000010", -- 27 VIC 068 |
"001110000111111110000000000001", -- 27 CPU 06C |
"001110000111111110000000000010", -- 28 VIC 070 |
"001110000111111110000000000001", -- 28 CPU 074 |
"001110000111111110000000000010", -- 29 VIC 078 |
"001110000111111110000000000001", -- 29 CPU 07C |
"011110000111111110000000000010", -- 30 VIC 080 |
"011110000111111110000000000001", -- 30 CPU 084 |
"011110000111111110000000000010", -- 31 VIC 088 |
"011110000111111110000000000001", -- 31 CPU 08C |
"011110000111111110000000000010", -- 32 VIC 090 |
"011110000111111110000000000001", -- 32 CPU 094 |
"011111000111111110000000000010", -- 33 VIC 098 |
"011110000111111110000000000001", -- 33 CPU 09C |
"011110000111111110000000000010", -- 34 VIC 0A0 |
"000110000111111110000000000001", -- 34 CPU 0A4 | 40 characters fetch
"000110000111111110000000000010", -- 35 VIC 0A8 |
"000110000111111110000000000001", -- 35 CPU 0AC |
"000110000111111110000000000010", -- 36 VIC 0B0 |
"001110000111111110000000000001", -- 36 CPU 0B4 |
"001110000111111110000000000010", -- 37 VIC 0B8 |
"001110000111111110000000000001", -- 37 CPU 0BC |
"001110000111111110000000000010", -- 38 VIC 0C0 |
"001110000111111110000000000001", -- 38 CPU 0C4 |
"001110000111111110000000000010", -- 39 VIC 0C8 |
"001110000111111110000000000001", -- 39 CPU 0CC |
"001110000111111110000000000010", -- 40 VIC 0D0 |
"001110000111111110000000000001", -- 40 CPU 0D4 |
"001110000111111110000000000010", -- 41 VIC 0D8 |
"001110000111111110000000000001", -- 41 CPU 0DC |
"001110000111111110000000000010", -- 42 VIC 0E0 |
"001110000111111110000000000001", -- 42 CPU 0E4 |
"001110000111111110000000000010", -- 43 VIC 0E8 |
"001110000111111110000000000001", -- 43 CPU 0EC |
"001110000111111110000000000010", -- 44 VIC 0F0 |
"001110000111111110000000000001", -- 44 CPU 0F4 |
"001110000111111110000000000010", -- 45 VIC 0F8 |
"001110000111111110000000000001", -- 45 CPU 0FC |
"001110000111111110000000000010", -- 46 VIC 100 |
"001110000111111110000000000001", -- 46 CPU 104 |
"001110000111111110000000000010", -- 47 VIC 108 |
"001110000111111110000000000001", -- 47 CPU 10C |
"001110000111111110000000000010", -- 48 VIC 110 |
"001110000111111110000000000001", -- 48 CPU 114 |
"001110000111111110000000000010", -- 49 VIC 118 |
"001110000111111110000000000001", -- 49 CPU 11C |
"001110000111111110000000000010", -- 50 VIC 120 |
"001110000111111110000000000001", -- 50 CPU 124 |
"001110000111111110000000000010", -- 51 VIC 128 |
"001110000111111110000000000001", -- 51 CPU 12C |
"001110000111111110000000000010", -- 52 VIC 130 |
"001110000111111110000000000001", -- 52 CPU 134 |
"001110000111111110000000000010", -- 53 VIC 138 |
"001110000111111110000000000001", -- 53 CPU 13C |
"001110000111111110000000000010", -- 54 VIC 140 |
"001110000111111110000000000001", -- 54 CPU 144 |
"001110000111111110000000010010", -- 55 VIC 148 /
"001110000111111111000000010000", -- 55 CPU 14C \
"001110000111111111000000011000", -- 56 VIC 150 |
"001110000111111111000000010000", -- 56 CPU 154 |
"001110000111111101000000001000", -- 57 VIC 158 |
"001110000111111101000000000000", -- 57 CPU 15C | Idle cycles
"001110000111111101000000001000", -- 58 VIC 160 |
"001110000111111101000000000000", -- 58 CPU 164 |
"001110000111111001000000001000", -- 59 VIC 168 |
"001110000111111001000000000000", -- 59 CPU 16C /
"001110001111111001000000100000", -- 60 VIC 170 \
"001110000111111001000001000000", -- 60 CPU 174 | Sprite #0 fetch
"001110000111110001000010000000", -- 61 VIC 178 |
"001110000111110001000100000000", -- 61 CPU 17C /
"001110000111110011001000100000", -- 62 VIC 180 \
"001110000111110011001001000000", -- 62 CPU 184 | Sprite #1 fetch
"011110000111100011001010000000", -- 63 VIC 188 |
"011110000111100011001100000000", -- 63 CPU 18C /
"011110000111100111010000100000", -- 64 VIC 190 \
"011100000111100111010001000000", -- 64 CPU 194 | Sprite #2 fetch
"011100000111000111010010000000", -- 65 VIC 198 |
"011100100111000111010100000000", -- 65 CPU 19C /
"011100000111001111011000100000", -- 01 VIC 1A0 \
"011100000111001111011001000000", -- 01 CPU 1A4 | Sprite #3 fetch
"000000000110001111011010000000", -- 02 VIC 1A8 |
"000000000110001111011100000000", -- 02 CPU 1AC /
"000000000110011111100000100000", -- 03 VIC 1B0 \
"000000000110011111100001000000", -- 03 CPU 1B4 | Sprite #4 fetch
"001000000100011111100010000000", -- 04 VIC 1B8 |
"001000000100011111100100000000", -- 04 CPU 1BC /
"001000000100111111101000100000", -- 05 VIC 1C0 \
"001000000100111111101001000000", -- 05 CPU 1C4 | Sprite #5 fetch
"001100000000111111101010000000", -- 06 VIC 1C8 |
"001100000000111111101100000000", -- 06 CPU 1CC /
"101100000001111111110000100000", -- 07 VIC 1D0 \
"101100000001111111110001000000", -- 07 CPU 1D4 | Sprite #6 fetch
"101100000001111111110010000000", -- 08 VIC 1D8 |
"101100000001111111110100000000", -- 08 CPU 1DC /
"101100000011111111111000100000", -- 09 VIC 1E0 \
"001100000011111111111001000000", -- 09 CPU 1E4 | Sprite #7 fetch
"001100000011111111111010000000", -- 10 VIC 1E8 |
"001110000011111111111100000000", -- 10 CPU 1EC /
"001110000111111111000000000100", -- 11 VIC 1F0 \
"001110000111111111000000000000", -- 11 CPU 1F4 |
"001110000111111110000000000100", -- 12 VIC 1F8 | Refresh
"001110000111111110000000000000", -- 12 CPU 1FC /
------------------------------------
-- PAL chip (63 cycles per line) --
------------------------------------
<...>
);
BEGIN
PROCESS(clock, addr, rdena)
BEGIN
IF (rising_edge(clock)) AND (rdena = '1') THEN
dout <= sched_rom(conv_integer(addr));
END IF;
END PROCESS;
END rtl;
I "stole" it from this excellent document :http://www.filegate.net/cbm/6-tech/pal_time.txt I am a bad guy :-D
-
@Gaula92 and FrenchShark
Amiga.org is such a lively and colorful place! There's more drama here than on a b-grade soap opera! I hate to admit it, but sometimes I surf this board just for the drama. Thanks for keeping it interesting!
Anytime dude. I am glad you like it.
In case you missed it, there is one piece here : http://www.minimig.net/viewtopic.php?f=9&t=552&start=30
hurry up before the admin deletes it.
Regards,
Frederic
-
Anytime dude. I am glad you like it.
In case you missed it, there is one piece here : http://www.minimig.net/viewtopic.php?f=9&t=552&start=30
hurry up before the admin deletes it.
Regards,
Frederic
Publishing snippets of code in a forum doesn't prove anything.
You're using Minimig code under the hood and you didn't publish the modified sources in exchange: that's ILLEGAL as the Minimig is GPL.
You actions and reactions speak for themselves.
-
Publishing snippets of code in a forum doesn't prove anything.
You're using Minimig code under the hood and you didn't publish the modified sources in exchange: that's ILLEGAL as the Minimig is GPL.
You actions and reactions speak for themselves.
I think I have the RIGHT to publish whatever I want from my work.
Since you do not know sh*t about verilog, I will explain to you WHY MY Agnus implementation is different from the Minimig one :
- One master clock at 86 MHz, the others clocks are just clock enable. Why 86 MHz ? because it is the SDRAM clock and 3 times the real Agnus master clock.
- One address generator instead of 6. It saves a lot of resource.
- DMA address related registers are stored in block RAM, it saves a lot of LUTs on Altera architecture.
- A DMA cache that saves 80% of the SDRAM bandwidth.
- It follows the Amiga bus timing : RGA on one cycle, DATA on the next cycle. It also has the early read feature for the Blitter D channel and the Floppy read. That also makes it incompatible with the Minimig chip ram bus.
- True short/long line in NTSC mode. May I remind you that the MCC216 has also a S-Video option ? So, not generating exactly 15734 Hz line rate in NTSC with the exact chroma frequency makes the TV displaying B&W.
- It takes only 10k LEs whereas the DE-1 one barely fits in 22k LEs (I must be a magician) :
http://i1359.photobucket.com/albums/q791/frenchshark/Core_size_zpscf2c088a.png.
Numbers speak for themselves.
How do I achieve that ? With reverse engineering:
http://i1359.photobucket.com/albums/q791/frenchshark/IMG_2972_zps7b329952.jpg
http://i1359.photobucket.com/albums/q791/frenchshark/IMG_2975_zps71b6e04b.jpg
(for example, it takes around 2 weeks to recreate Denise)
Thanks to a friend I have also a C64, an Atari ST and an A500 I can experiment with.
So, one day there will be an Atari ST core but I am sure that gaula92 will say that it got stolen from somewhere else.
Internet if full of stupid people.
too bad.
Frederic
-
I think I have the RIGHT to publish whatever I want from my work.
not when it involves GPL code you've modified. by modifying the minimig core to add your own agnus core, your agnus core becomes GPL code because you have made a derivative work of a GPL work.
The GPL requires release/publication of all derivative works when asked for it.
The GPL is what allowed you to use the minimig core in the first place. The GPL requires you give back all your changes.
Congrats for writing a new agnus core, I'm sure its not easy, and your doing a lot of hard work on your device, but that does not make you compliant with the GPL.
-
not when it involves GPL code you've modified. by modifying the minimig core to add your own agnus core, your agnus core becomes GPL code because you have made a derivative work of a GPL work.
The GPL requires release/publication of all derivative works when asked for it.
The GPL is what allowed you to use the minimig core in the first place. The GPL requires you give back all your changes.
Congrats for writing a new agnus core, I'm sure its not easy, and your doing a lot of hard work on your device, but that does not make you compliant with the GPL.
Maybe you do not get it : I have my own Paula, Denise, Agnus and Gary, it is not derivative work.
The Agnus chip I wrote cannot work with the Minimig HDL : different clocking scheme, different bus protocol. The same for Paula and Denise. Gary is designed to interface with a SDRAM controller and has autoconfig logic for Fast RAM. Between Gary and the chipset, there is a DMA cache.
I started with Denise (see the previous links), then Paula. I ran the two chips on my A2000 HW with different games and demos.
After that I wrote Agnus and simulate the 3 chips together using test copperlist.
BTW, the neat feature on the Amiga is that you can exercise the chipset without a 68000.
Finally I wrote Gary and the 8520 then connected the J68 core.
And I have done more simulations like this one :
http://i1359.photobucket.com/albums/q791/frenchshark/snapshot0111_boot_menu_3_zps541996cc.png?t=1364648469
Not one verilog module is from Minimig source.
-
Maybe you do not get it : I have my own Paula, Denise, Agnus and Gary, it is not derivative work.
Thay may be true for an unreleased core, but the core running in your commercial product HAS BEEN a primitive Minimig for almost two years.
You have been selling a product with GPL code closed and expanded without opening back the sources.
And the fact that this product is badly built is just and additional problem.
You also left the buyers of your product without support or updates: people having problems with the C64 core were left without critical fixes, and the Amiga core stalled for almost two years also.
Even when you offered some kind of support, that irritating Retrofan with stupid phrases like "long live retro!" and no technical knowledge was all we got.
No: this is NO WAY of dealing with users. Look at other projects, like MikeJ's FPGA Arcade, Turbo Chameleon 64 or the original Minimig V1.1 board: thanks to their transparent, open-source nature, we are getting mature and stable products with a good and active community behind them.
In the other hand, your product is obscure, unsupported and faulty after all this time. You get what you deserve.
-
Thay may be true for an unreleased core, but the core running in your commercial product HAS BEEN a primitive Minimig for almost two years.
You have been selling a product with GPL code closed and expanded without opening back the sources.
Finally, is it primitive or expanded ? Do you want the modified Minimig ? Fine, you will just discover that all the modifications were already posted on the minimig.net website.
Minimig is also a commercial product and it will cost you just the double to get only a board (if you can find one).
Do you really think I am making money doing that ?
And the fact that this product is badly built is just and additional problem.
You also left the buyers of your product without support or updates: people having problems with the C64 core were left without critical fixes, and the Amiga core stalled for almost two years also.
Critical fixes on the C64 ? On lot of points, it is better than the others cores.
I know I have one bug on the sprites and one on the scrolling. It is just an issue for some tricky demos and few games.
I cannot work on everything 24/7, I have a life. Moreover, I do not get motivated when I read your BS.
Even when you offered some kind of support, that irritating Retrofan with stupid phrases like "long live retro!" and no technical knowledge was all we got.
I am not responsible of others' behaviours.
No: this is NO WAY of dealing with users. Look at other projects, like MikeJ's FPGA Arcade, Turbo Chameleon 64 or the original Minimig V1.1 board: thanks to their transparent, open-source nature, we are getting mature and stable products with a good and active community behind them.
In the other hand, your product is obscure, unsupported and faulty after all this time. You get what you deserve.
It looks like you are the only one spreading your sh*t on the forums. I get positive feedback from a lot of people.
-
Finally, is it primitive or expanded ?
Primitive in the sense that you took an early Minimig core and expanded (adapted) it to work with your product.
I don't think you get much positive feedback: ask other MCC-216 users around in the Lemon64 forums, where you started announcing your product years ago, if you dare.
Bashing me won't change these facts:
"Your currently available Amiga core, wich has been available for almost two years, and wich you SOLD as part of your product, is a modified Minimig core, and is ILLEGAL as you never released the sources, even if you are working on your own Minimig implementation now".
"You chose cheap materials and the MCC-216 is easy to break: power button, power supply are very bad quality"
"You and Retrofan retired from the unofficial support forums months ago, thus leaving users without any kind of support, with broken cores."
Now if someone gives positive feedback, well, better for you. But I wouldn't recommend anything from you and I for one will stay away from whatever you come up with. There are FAR better alternatives.
As an angered ex-mcc216 owner, my hatred comes from your actions. I don't know you nor had anything against you to begin with. If you had proceeded as expected (by opening up your modified Minimig sources, fixing critical C64 bugs like keyboard problems and disk writting, etc) I would be a proud user giving good feedback as I do with the Minimig V1.1 board, the FPGA Arcade or the TC64, wich are great products.
You have been claiming that your product is also an AppleII implementation. You advertise it as souch here:
http://arcaderetrogaming.com/shop/category_100/ClassicComputer.html?sessid=iAfQ4wXcKUTiBSvQrUBQREQhvRV8zBwrp0kisg6KYhqh0s1jP7klTm2cp3P9LKjY&shop_param=cid%3D%26
..but the sad fact is that it won't even load an AppleII disk image.
Should we ask AppleII core developer what he thinks about you, by the way? Do you want me to ask him and post the answer here? ;)
I'm not spreading s h i t: after being scammed once, I'm just trying to inform other people about what you did so they can judge.
-
Primitive in the sense that you took an early Minimig core and expanded (adapted) it to work with your product.
I don't think you get much positive feedback: ask other MCC-216 users around in the Lemon64 forums, where you started announcing your product years ago, if you dare.
Bashing me won't change these facts:
"Your currently available Amiga core, wich has been available for almost two years, and wich you SOLD as part of your product, is a modified Minimig core, and is ILLEGAL as you never released the sources, even if you are working on your own Minimig implementation now".
Amiga core is not SOLD, it is just free of charge, like others cores.
If you have to pay extra for some cores, it is because of software licensing (ROM, games, etc...). You can buy the bare stuff and populate the SD-Card with the necessary cores and files if you know how to get the files.
"You chose cheap materials and the MCC-216 is easy to break: power button, power supply are very bad quality"
$1.34 for a switch I do not call that cheap.
http://octopart.com/r13-529bl-05-bgg-shin+chin-20074423
Price does not mean quality anymore with 90% of electronics parts coming from china.
"You and Retrofan retired from the unofficial support forums months ago, thus leaving users without any kind of support, with broken cores."
Now if someone gives positive feedback, well, better for you. But I wouldn't recommend anything from you and I for one will stay away from whatever you come up with. There are FAR better alternatives.
That's great I will not get any more complains then.
As an angered ex-mcc216 owner, my hatred comes from your actions. I don't know you nor had anything against you to begin with. If you had proceeded as expected (by opening up your modified Minimig sources, fixing critical C64 bugs like keyboard problems and disk writting, etc) I would be a proud user giving good feedback as I do with the Minimig V1.1 board, the FPGA Arcade or the TC64, wich are great products.
You have been claiming that your product is also an AppleII implementation. You advertise it as souch here:
http://arcaderetrogaming.com/shop/category_100/ClassicComputer.html?sessid=iAfQ4wXcKUTiBSvQrUBQREQhvRV8zBwrp0kisg6KYhqh0s1jP7klTm2cp3P9LKjY&shop_param=cid%3D%26
..but the sad fact is that it won't even load an AppleII disk image.
Should we ask AppleII core developer what he thinks about you, by the way? Do you want me to ask him and post the answer here? ;)
I'm not spreading s h i t: after being scammed once, I'm just trying to inform other people about what you did so they can judge.
I was in contact with Alex. I gave him all that was necessary for porting the core.
I did not write the apple 2 core. If he has something to say, he can send me an e-mail.
You can post whatever you want here : just be cautious there are forum rules so do not cross the red line.
-
Hi. I am a happy owner of three MCC-216 VGA and one MCC-216 S-Video.
I mostly use them with the C64 core done by Frenchshark, and will start tinkering with the Amiga core once it is launched.
The C64 core works pretty well with old and new C64 games, some of the most important features it has are:
- PAL and NTSC C64 models supported
- Stereo 8580 SIDs support with filters
- Perfect smooth scrolling if your monitor supports the MCC resolutions / refresh frequencies
- 1541 emulation with read and write support of D64 images, with good compatibility with fast loaders
- Support of mount of up to 10 d64 images for multi disk games
- Very fast reset and startup of the C64 core: less than 4 seconds boot including the d64 images mount
- Supports very well the JiffyDOS rom and JiffyDOS 1541II rom for fast loading of d64 images
- Swap joysticks feature (swap ports 1 <-> port 2): only needs one joystick
- Proprietary USB joypad support
- Mouse support (PS2 mouse)
- Very nice and colorful menu for selecting the games / disc images
- Very good games compatibility (above 90% based on tested games)
I wrote down an article on lemon64 forum with some tips for using the C64 core, it has almost all you need to know to use it (strengths and weaknesses too), you can read it here:
http://www.lemon64.com/forum/viewtopic.php?t=34194&start=550
The MCC-216 works very well for me and for many other people, you can check the customer’s feedback from Ebay buyers:
http://feedback.ebay.com/ws/eBayISAPI.dll?ViewFeedback2&userid=arcaderetrogaming&ftab=AllFeedback&myworld=true
For a C64 fan that wants to run games on new hardware I would definitively recommend it, and I expect that the new Amiga core that it is coming will be great too.
Regards, Juan
-
Hi. I am a happy owner of three MCC-216 VGA and one MCC-216 S-Video.
I mostly use them with the C64 core done by Frenchshark, and will start tinkering with the Amiga core once it is launched.
The C64 core works pretty well with old and new C64 games, some of the most important features it has are:
- PAL and NTSC C64 models supported
- Stereo 8580 SIDs support with filters
- Perfect smooth scrolling if your monitor supports the MCC resolutions / refresh frequencies
- 1541 emulation with read and write support of D64 images, with good compatibility with fast loaders
- Support of mount of up to 10 d64 images for multi disk games
- Very fast reset and startup of the C64 core: less than 4 seconds boot including the d64 images mount
- Supports very well the JiffyDOS rom and JiffyDOS 1541II rom for fast loading of d64 images
- Swap joysticks feature (swap ports 1 <-> port 2): only needs one joystick
- Proprietary USB joypad support
- Mouse support (PS2 mouse)
- Very nice and colorful menu for selecting the games / disc images
- Very good games compatibility (above 90% based on tested games)
I wrote down an article on lemon64 forum with some tips for using the C64 core, it has almost all you need to know to use it (strengths and weaknesses too), you can read it here:
http://www.lemon64.com/forum/viewtopic.php?t=34194&start=550
The MCC-216 works very well for me and for many other people, you can check the customer’s feedback from Ebay buyers:
http://feedback.ebay.com/ws/eBayISAPI.dll?ViewFeedback2&userid=arcaderetrogaming&ftab=AllFeedback&myworld=true
For a C64 fan that wants to run games on new hardware I would definitively recommend it, and I expect that the new Amiga core that it is coming will be great too.
Regards, Juan
Thanks Juan. You don't have to to do that.
Be careful you will get some bashing from some guys here :-).
Moreover, your only 3-post count will look suspicious, maybe it is me writing this comment :-)
Anyway, with any product, you cannot get 100% of the customers happy, that's a rule.
Regards,
Frederic
-
Thanks Juan. You don't have to to do that.
Be careful you will get some bashing from some guys here :-).
Moreover, your only 3-post count will look suspicious, maybe it is me writing this comment :-)
Anyway, with any product, you cannot get 100% of the customers happy, that's a rule.
Regards,
Frederic
Hi Frederic, no problem!
Don't worry, I am only saying that I like the MCC and the features it has.
Little posts here, I only come to learn about the Amiga since I only had a VIC20 and a C64 on the golden 8-bit years.
Keep the good work and I hope to see tha launch of the Amiga core soon!
:) :) :)
-
Be careful you will get some bashing from some guys here :-).
That's nonsense. juga didn't sell me a piece of junk with defective cores based on GPL ones without releasing the modified sources and easy-to-break components. He's just another user, with a different point of view about your product, that's all. I'm not bashing him and your insinuation is very irritating and unnecessary.
He may not care about support, bug-fixing or quality, but I respect him because he hasn't fooled me like you do with your advertisement and your product.
I mostly use them with the C64 core done by Frenchshark, and will start tinkering with the Amiga core once it is launched.
The Amiga core for the MCC-216 was launched almost two years ago (and I'm sure you know it). It's an illegal core based on GPL code. Even if a new core is to be released in the future based on original work, that doesn't change the former fact.
And even then, frenchshark, most TG68 incompatibilities will have been addressed and I won't have a reason to believe you: you can fool me once, but not twice.
And as I said, I hope real developers will try hard to stop you.
-
So the original MCC Amiga was based upon the Minimig sources? And those source changes were posted back to minimig.net, or not? The existing Amiga core would only infringe copyright if the source changes (to make it run on the MCC) were not published, and made available upon request (e.g., download of the source).
The new Amiga core is a totally new implementation, once it is released, with no Minimig (or other GPL) components?
I'm just trying to understand here, because the allegations being made are quite serious.
-
tl;dr, anybody who does anything Amiga related in Verilog is going to be accused of ripping off Minimig. What a shame.
-
So the original MCC Amiga was based upon the Minimig sources?
Yes. There's a new version in the works, apparently, but current Amiga core is Minimig-based.
The existing Amiga core would only infringe copyright if the source changes (to make it run on the MCC) were not published, and made available upon request (e.g., download of the source).
That's the situation.
And those source changes were posted back to minimig.net, or not?
No. He posted some small pieces of code on minimig.net, but not the complete sources. Not by far. That's why no one could fix the current implementation for the last two years, and that's why it's illegal.
-
The Amiga core for the MCC-216 was launched almost two years ago (and I'm sure you know it).
Yes, you are right.
I don't use this beta Amiga core (of course I have tested it), I am waiting for the new Amiga core for using the Amiga emulation on the MCC.
-
tl;dr, anybody who does anything Amiga related in Verilog is going to be accused of ripping off Minimig. What a shame.
This is confusing. There's no "ripping off", but GPL violation here. Don't try to confuse people.
-
This is confusing. There's no "ripping off", but GPL violation here. Don't try to confuse people.
That's BS. You're accusing this guy of ripping off other people's work and not giving back as evidenced by quite a few posts of yours across multiple forums. You've taken this well beyond a simple polite discussion about GPL compliance.
-
@gaula92
Thay may be true for an unreleased core, but the core running in your commercial product HAS BEEN a primitive Minimig for almost two years.
You have been selling a product with GPL code closed and expanded without opening back the sources.
And the fact that this product is badly built is just and additional problem.
And your problem with this is? People create and sell poorly designed products all the time and people will still buy them....but as for Frederic's product being poorly designed, I don't think most of us on this board have the qualifications to make that kind of statement, yourself included.
And your accusations about GPL violations are off-base as well. People write closed-source applications and modules all the time that interface with open sourced and GPL code. This same issue is being addressed with Nvidia Optimus technology on Linux platforms, so I don't see why you're trying to make this an issue except that you have some sort of immature personal grudge match that you've declared.
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Not sure of the benefit of a c128 over a c64. I had a 128d for 3 years back in (well a long time ago) and used its 128 mode sparingly. I did use CPM a little though.
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And your accusations about GPL violations are off-base as well. People write closed-source applications and modules all the time that interface with open sourced and GPL code. This same issue is being addressed with Nvidia Optimus technology on Linux platforms, so I don't see why you're trying to make this an issue except that you have some sort of immature personal grudge match that you've declared.
A lot of people consider that NVidia violate the GPL. But they link their modules in a way that they think gets them round it, they are tolerated because nobody wants to sue and NVidia are producing drivers.
If any changes have been made to the minimig code to make it work on the MCC then not releasing the changes is a blatant violation. Whether you class that as ripping off or not is semantics.
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@psxphill
I really don't care what some people "consider" a violation. I only care about the facts. And all I've seen here is gaula92 using this thread as a personal attack directed at Frederic. Until someone cares enough to PROVE with facts that Frederic is violating the GPL, then they need to shut up and stop attacking his credibility while hiding behind an online forum. If gaula92 is so convinced that Frederic has violated the GPL, and he has proof of it, then he should file a law suit instead of turning this thread into a weapon for personal attacks. Where I come from, that's called "Put up, or shut up!" Right now I'd like a lot of "Shut Up" as far as this matter and GPL violations are concerned.
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Until someone cares enough to PROVE with facts that Frederic is violating the GPL, then they need to shut up and stop attacking his credibility while hiding behind an online forum.
I don't think there is any dispute that MCC uses minimig source, MCC doesn't provide any source. Well I think that raises enough doubt that there is a violation that discussion online is fine.
If gaula92 is so convinced that Frederic has violated the GPL, and he has proof of it, then he should file a law suit instead of turning this thread into a weapon for personal attacks. Where I come from, that's called "Put up, or shut up!" Right now I'd like a lot of "Shut Up" as far as this matter and GPL violations are concerned.
I think suggesting filing a law suit is unhelpful.
I'm not using personal attacks & I think discussion of GPL violations is fine. You don't have to read it.
Of course you could argue that it's off topic for this thread.
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Current beta Amiga core for the MCC-216 is, in fact, a Minimig core port. A new core, unrelated to Minimig, is in the works, but the core published almost two years ago is Minimig based. Frenchshark didn't have anything as advanced back then: he used to report advancements in the unofficial MCC-216 forum (retrorebooted.com, now offline) and I remember the situation perfectly, as anybody who was at that forum does.
He announced he was starting his own 68K soft-cpu and chipset implementations AFTER the core was published.
And no, I won't be going for a lawsuit as I don't care about the MCC-216 anymore: I believe time puts people in the place they should be. I feel scammed by the low quality of the thing, the broken cores announced as "supportedd systems" (like the lame AppleII situation where it can't even load a disk image because the original core author won't touch the MCC-216 with a 10mts pole anymore) and the lack of fixed and the general support (or lack of).
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@psxphill
I really don't care what some people "consider" a violation. I only care about the facts. And all I've seen here is gaula92 using this thread as a personal attack directed at Frederic. Until someone cares enough to PROVE with facts that Frederic is violating the GPL, then they need to shut up and stop attacking his credibility while hiding behind an online forum. If gaula92 is so convinced that Frederic has violated the GPL, and he has proof of it, then he should file a law suit instead of turning this thread into a weapon for personal attacks. Where I come from, that's called "Put up, or shut up!" Right now I'd like a lot of "Shut Up" as far as this matter and GPL violations are concerned.
The only person that can file a lawsuit is the owner of the minimig source copyright - which is probably a combination of Dennis, yaqube and other people who have contributed to it over the years. The fact that they're not exactly screaming about this violation probably says a lot.
However I do think that the full sources to the minimig-derived core should be made available as per the license requirements, and I don't see the harm in releasing it.
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The fact that they're not exactly screaming about this violation probably says a lot.
If they didn't care then I would have expected MCC to ask for a non GPL licensed version of the code so that they didn't have to provide source. If they'd done that then I'd have expected MCC to shout loudly that they had permission.
I'm not sure why Dennis wouldn't enforce the license, the FSF will usually help out. Faced with the prospect of a lawsuit then most people just release the source.
The biggest failing of the MCC is that they didn't open source everything & made it easy for anyone to develop for it, I would have bought one if they had.
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ugh.
I think I will buy a Ouya when it comes out. It is open to devs.
But, I could change my mind though.
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@all
Let me give you some technical insight on the MCC.
It has a unique feature : it does not have any configuration controller (such as a ARM or a PIC chip).
The FPGA is its own configuration controller thanks to the "Remote update" feature of the Cyclone III.
This has some consequences :
- If the "bootloader" that is responsible of loading the others cores is erased from the flash, the device does not start anymore.
- Some safeguards must be put in place in the cores' bitstreams to prevent the user from doing "stupid" things.
So, it is very difficult to open the platform to anybody.
As for the Minimig core, I told you already that I posted the modifications on minimig.net.
If anybody wants to get the HDL source, just send me a PM, I will send the archive.
A quick overview of the sources:
- YQ091224 Minimig source with changes in 8520 CIA and Paula/Floppy.
- TG68
- VHDL top level / wrapper
As for the "OSD" CPU in the design, it is NIOS based. Just ask Altera for the GPL source code. Good luck ;-).
PS: sorry for the C128 lovers to have hijacked your thread.
Regards,
Frederic
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As for the Minimig core, I told you already that I posted the modifications on minimig.net.
If anybody wants to get the HDL source, just send me a PM, I will send the archive.
So even you finally recognize here that current Amiga core IS a Minimig adaptation (as Retrofan and you implicitly said many times in the past).
As an user, and one who bought not one but three of your MCC-216 machines, I see it a step in the right direction.
So, it is very difficult to open the platform to anybody.
Wrong. Open it. Open it as much as you can, and for your own good, FACILITATE the work to let others to port cores to your platform and fix the cores.
Look: if you had opened it back in 2011, you'd have a VERY good Amiga core by now, open and legal, because the community would have found incompatibilites and developers would have fixed them. If you try current Altera DE1 Minimig, you'll see it's FAR superior to your outdated, broken Amiga core. That's because geniuses like Mmrobinsonb5, Boing400, Chaos and many other experts have addressed bugs and made it the wonder it's today.
You would also have a great Spectrum 128K core, and possibly many of the arcade cores the Chameleon 64 is receiving these days.
Your product would be admired and awaited as we admire the FPGA Arcade or the Minimig V1.1 board, because these products are not just funny but also exciting to explore, learn and try wild new cores on them, with unexpected results.
On the other hand, the MCC-216 remains obscure, unknown, not very attractive at all with outdated cores an NO POSSIBILITY for the community to fix them.
I suppose you had a different business model in mind when you started the MCC-216 project: maybe you wanted to sell the cores, or the games licensed by these Cloanto vultures, but as you can see, that's not going to work. No way.
Maybe you're in time, Frenchshark, and you can still open the damn thing and let people help themselves and help YOU, and make the MCC-216 a good product, not some obscure platform using illegal cores (but please replace the materials ASAP).
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Hi Frederic, how are you.
How is going the new Amiga core for the MCC?
What features will it have? Like kickstarts supported, configurable parameters (memory...), HDF support, OCS or ECS, etc.
Regards, Juan
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I change my mind to a C65. I guess it would not be as tough as a complete C128.