While the slot is 64 bit the DIMM memory modules are often made up of 8 or 16 bit IC's which are controlled by the DQMB lines on the SD-Ram connector.
There are 8 DQMB lines, enough for 8bit control of the 64bit bus, technically you could interface an 8bit CPU to the SD-Ram, the down side is like I said, some are chained as 16bit, some I think even 32 but Im 90% sure there are no 64bit only DIMM's.
Some good reading on SD-Ram DIMM layouts is available from this document:
PC133 SDRAM Registered DIMM Design Specification Revision 1.1And for a more techincal doc on how SD-Ram works you need to read this:
PC SDRAM Specification Revision 1.7The only reason why some MINIMAL logic would be required with PSRAM, as far as I know, is the autoconfig procedure.
Your memory speed would such, you will need to implement a burst system.. which is Z3 specific (Well its based on the 030 bus burst system but you know...) and without that its one read or write per bus cycle vs four using burst.
Also Z3 has a multiplexed bus, the data and address busses are the same thing, it just has an address phase and data phase, your going to need the full array of bus buffers and latches to decode that.
Its still going to be a big job... your best bet would be to get a nice big CPLD or FPGA and connect the Zorro bus to one end and the SD-Ram slot to the other then work everything out in software.
Final edit: As a little example Eclipse computers (A cheap ass UK computer company) is selling a
512Meg SD-Ram DIMM for £30 and they list it as a 16 chip module with each chip having 32meg and an 8 bit bus. Which technically gives a 128bit bus, so every two chips must be coupled to the same DQMB line, giving a 16bit CPU bus, taa dahh.
So who's making a Z2 version? (I joke, although you could have a rather nifty 8meg SD-Ram upgrade card working on an A2000)