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General chat about Amiga topics / Spam! Re: Optimal Сasual Dating - Authentic Damsels
« Last post by AndyFC on April 24, 2024, 07:09:01 AM »Reported
I need to replace some SIMM sockets on an memory/SCSI card, I think I can get away with 4 slots, but ideally I'd replace all 16 slots.
There is a WODEM called new serial to WLAN adapter recently released, but it is not as fast as you would like it to be.
I'd prefer the PCMCIA solution or maybe a ClockPort card, the a314cp as an exotic solution.
Since you have a tower case there might be an option to add a bus board to it.
may not be a proper E clock because of the 60/40 duty cycleSo about that... I've been looking at these signals with my scope (and also read some more of the 68000 datasheet), and the shocking observation I made regarding the 14MHz accelerator in OP that the flip flop (74x112) used to divide the E frequency from the processor is falling edge triggered! Meaning the E signal it outputs is delayed by the 4 processor clock cycles (of the 10 in the 6/4 duty cycle split) and rises on the falling edge of processor E! (That doesn't seem right, but somehow it works.) Likewise it is not 60/40 duty cycle but 50/50 as generated by the flip flop divider. This raises a lot of questions... Why does it work like this (50/50) and how important is the 60/40 duty cycle? Does it not matter that the edges of the E clock that the Amiga sees are not edge aligned with the E generated by the processor, or does 68000 just not care?
VMA timing may need some wait states or at least latching with the 7 MHz clock.What I read in the 68000 datasheet is that it's synchronized with E, I'll need to check with the scope which edge it's in sync with because the datasheet doesn't say.
Also, you need logic (often described as 68000 state machine logic) to guarantee at least one 7 MHz wait state on the 68000 Address Strobe, Dtack sampling on the third 7 MHz clock and cycle termination on the falling edge of the last 7 MHz clock. The reason I am warning you about Dtack sampling on the third 7 MHz clock is because Commodore allowed sloppy Zorro2 designs with early Dtack generation. Note: The Upper and Lower Data strobes may or may not need to be delayed on write cycles.Wow, lots useful info, thanks!
Now, just in case that's not enough to consider, the 68000 state machine logic needs to handle the bus arbitration signals with the proper 7 MHz timing too!