may not be a proper E clock because of the 60/40 duty cycle
So about that... I've been looking at these signals with my scope (and also read some more of the 68000 datasheet), and the
shocking observation I made regarding the 14MHz accelerator in OP that the flip flop (74x112) used to divide the E frequency from the processor is falling edge triggered! Meaning the E signal it outputs is delayed by the 4 processor clock cycles (of the 10 in the 6/4 duty cycle split) and rises on the falling edge of processor E! (That doesn't seem right, but somehow it works.) Likewise it is not 60/40 duty cycle but 50/50 as generated by the flip flop divider. This raises a lot of questions... Why does it work like this (50/50) and how important is the 60/40 duty cycle? Does it not matter that the edges of the E clock that the Amiga sees are not edge aligned with the E generated by the processor, or does 68000 just not care?
VMA timing may need some wait states or at least latching with the 7 MHz clock.
What I read in the 68000 datasheet is that it's synchronized with E, I'll need to check with the scope which edge it's in sync with because the datasheet doesn't say.
The 14MHz accelerator in OP latches VMA/VPA on the 1.4MHz E clock from the processor. That's probably not right either.
Also, you need logic (often described as 68000 state machine logic) to guarantee at least one 7 MHz wait state on the 68000 Address Strobe, Dtack sampling on the third 7 MHz clock and cycle termination on the falling edge of the last 7 MHz clock. The reason I am warning you about Dtack sampling on the third 7 MHz clock is because Commodore allowed sloppy Zorro2 designs with early Dtack generation. Note: The Upper and Lower Data strobes may or may not need to be delayed on write cycles.
Now, just in case that's not enough to consider, the 68000 state machine logic needs to handle the bus arbitration signals with the proper 7 MHz timing too! 
Wow, lots useful info, thanks!
There are likely a lot of timing violations in the 14MHz accelerator in OP. But somehow it was working even at 28MHz. But so far my attempts at changes to the E signal generation all resulted in a bright green or a black screen. I even tried positive edge triggered flip flops for the divider so the rising edge would be aligned with the rising edge of E from the processor, but that did not produce a working result. I will try a few more things I thought of and also make a timing diagram of what I see and what I did, or maybe a picture from my scope for the next post.
The only things I have been changing right now is the generation of the E signal and sometimes latching of VMA/VPA. Just this change alone causes the breakage, I think it's best I focus on this one thing at a time?
Recent Posts